[Mesa-stable] [PATCH 2/3] i965/gen6/blorp: Set need_workaround_flush at top of blorp

[Chad Versace]

Unconditionally set brw->need_workaround_flush at the top of gen6 blorp
state emission. This is an extra safety measure to prevent undiscovered
difficult-to-diagnose gpu hangs.

The art of emitting workaround flushes on Sandybridge is mysterious and
not fully understood. Ken and I believe that
intel_emit_post_sync_nonzero_flush() may be required when switching from
regular drawing to blorp.

CC: mesa-stable at lists.freedesktop.org
CC: Kenneth Graunke <kenneth at whitecape.org>
CC: Paul Berry <stereotype441 at gmail.com>
CC: Stéphane Marchesin <marcheu at chromium.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
---
 src/mesa/drivers/dri/i965/gen6_blorp.cpp | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 929d7b5..9db0840 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -1023,7 +1023,6 @@ gen6_emit_hiz_workaround(struct brw_context *brw, enum gen6_hiz_op hiz_op)
     */
    if (hiz_op == GEN6_HIZ_OP_DEPTH_RESOLVE ||
        hiz_op == GEN6_HIZ_OP_HIZ_RESOLVE) {
-      brw->batch.need_workaround_flush = true;
       intel_emit_post_sync_nonzero_flush(brw);
       intel_emit_depth_stall_flushes(brw);
    }
@@ -1051,6 +1050,9 @@ gen6_blorp_exec(struct brw_context *brw,
 
    uint32_t prog_offset = params->get_wm_prog(brw, &prog_data);
 
+   /* Emit workaround flushes when we switch from drawing to blorping. */
+   brw->batch.need_workaround_flush = true;
+
    gen6_emit_hiz_workaround(brw, params->hiz_op);
    gen6_emit_3dstate_multisample(brw, params->dst.num_samples);
    gen6_emit_3dstate_sample_mask(brw,
-- 
1.8.5.2