[Mesa-stable] [PATCH 1/2] i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions.

[Anuj Phogat]

On Tue, Apr 21, 2015 at 10:13 PM, Kenneth Graunke <kenneth at whitecape.org> wrote:
> The BLT engine on Gen8+ requires linear surfaces to be cacheline
> aligned.  This restriction was added as part of converting the BLT to
> use 48-bit addressing.
>
> intel_emit_linear_blit needs to handle blits that are not cacheline
> aligned, as we use it for arbitrary glBufferSubData calls and subrange
> mappings.
>
> Since intel_emit_linear_blit uses 1 byte per pixel, we can use the src/dst
> pixel X offset field to represent the unaligned portion, and subtract
> that from the address so it's cacheline aligned.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88521
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> Cc: mesa-stable at lists.freedesktop.org
> ---
>  src/mesa/drivers/dri/i965/intel_blit.c | 22 ++++++++++++++--------
>  1 file changed, 14 insertions(+), 8 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
> index 4993f60..98d414c 100644
> --- a/src/mesa/drivers/dri/i965/intel_blit.c
> +++ b/src/mesa/drivers/dri/i965/intel_blit.c
> @@ -524,6 +524,7 @@ intel_emit_linear_blit(struct brw_context *brw,
>  {
>     struct gl_context *ctx = &brw->ctx;
>     GLuint pitch, height;
> +   int16_t src_x, dst_x;
>     bool ok;
>
>     /* The pitch given to the GPU must be DWORD aligned, and
> @@ -532,11 +533,13 @@ intel_emit_linear_blit(struct brw_context *brw,
>      */
>     pitch = ROUND_DOWN_TO(MIN2(size, (1 << 15) - 1), 4);
>     height = (pitch == 0) ? 1 : size / pitch;
> +   src_x = src_offset % 64;
> +   dst_x = dst_offset % 64;
>     ok = intelEmitCopyBlit(brw, 1,
> -                         pitch, src_bo, src_offset, I915_TILING_NONE,
> -                         pitch, dst_bo, dst_offset, I915_TILING_NONE,
> -                         0, 0, /* src x/y */
> -                         0, 0, /* dst x/y */
> +                         pitch, src_bo, src_offset - src_x, I915_TILING_NONE,
> +                         pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE,
> +                         src_x, 0, /* src x/y */
> +                         dst_x, 0, /* dst x/y */
>                           pitch, height, /* w, h */
>                           GL_COPY);
>     if (!ok)
> @@ -544,15 +547,18 @@ intel_emit_linear_blit(struct brw_context *brw,
>
>     src_offset += pitch * height;
>     dst_offset += pitch * height;
> +   src_x = src_offset % 64;
> +   dst_x = dst_offset % 64;
>     size -= pitch * height;
>     assert (size < (1 << 15));
>     pitch = ALIGN(size, 4);
> +
>     if (size != 0) {
>        ok = intelEmitCopyBlit(brw, 1,
> -                            pitch, src_bo, src_offset, I915_TILING_NONE,
> -                            pitch, dst_bo, dst_offset, I915_TILING_NONE,
> -                            0, 0, /* src x/y */
> -                            0, 0, /* dst x/y */
> +                            pitch, src_bo, src_offset - src_x, I915_TILING_NONE,
> +                            pitch, dst_bo, dst_offset - dst_x, I915_TILING_NONE,
> +                            src_x, 0, /* src x/y */
> +                            dst_x, 0, /* dst x/y */
>                              size, 1, /* w, h */
>                              GL_COPY);
>        if (!ok)
> --
> 2.3.5
>
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> mesa-stable mailing list
> mesa-stable at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/mesa-stable

I had a patch which imposed these alignment restrictions in blitter.
But, it caused hangs in piglit run. I was missing the patch 1
of your series. I'm glad you fixed it.

Both patches are:
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>