[Mesa-stable] [Mesa-dev] [PATCH] i965: Split Gen4-5 BlitFramebuffer code; prefer BLT over Meta.

[Jordan Justen]

Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

On 2015-03-04 20:44:19, Kenneth Graunke wrote:
> A while back I switched intel_blit_framebuffer to prefer Meta over the
> BLT.  This meant that Gen8 platforms would start using the 3D engine
> for blits, just like we do on Gen6-7.5.
> 
> However, I hadn't considered Gen4-5 when making that change.  The BLT
> engine appears to be substantially faster on 965GM than using Meta to
> drive the 3D engine.  This isn't too surprising: original Gen4 doesn't
> support tile offsets (that came on G45), and the level/layer fields
> don't work for cubemap rendering, so for inconvenient miplevel
> alignments, we end up blitting or copying data to/from temporaries
> in order to render to it.  We may as well just use the blitter.
> 
> I chose to use the BLT on Gen4-5 because they use the same ring for
> both 3D and BLT; Gen6+ splits it out.
> 
> Fixes regressions on 965GM due to botched tile offset code (we should
> fix those properly as well, but they're longstanding bugs - for now,
> put things back to the status quo).
> 
> Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89430
> Cc: "10.5" <mesa-stable at lists.freedesktop.org>
> Cc: Mark Janes <mark.a.janes at intel.com>
> ---
>  src/mesa/drivers/dri/i965/intel_fbo.c | 50 ++++++++++++++++++++++++++++++++++-
>  1 file changed, 49 insertions(+), 1 deletion(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
> index 04e5030..121c97f 100644
> --- a/src/mesa/drivers/dri/i965/intel_fbo.c
> +++ b/src/mesa/drivers/dri/i965/intel_fbo.c
> @@ -916,6 +916,51 @@ intel_blit_framebuffer(struct gl_context *ctx,
>  }
>  
>  /**
> + * Gen4-5 implementation of glBlitFrameBuffer().
> + *
> + * Tries BLT, Meta, then swrast.
> + *
> + * Gen4-5 have a single ring for both 3D and BLT operations, so there's no
> + * inter-ring synchronization issues like on Gen6+.  It is apparently faster
> + * than using the 3D pipeline.  Original Gen4 also has to rebase and copy
> + * miptree slices in order to render to unaligned locations.
> + */
> +static void
> +gen4_blit_framebuffer(struct gl_context *ctx,
> +                      struct gl_framebuffer *readFb,
> +                      struct gl_framebuffer *drawFb,
> +                      GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
> +                      GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
> +                      GLbitfield mask, GLenum filter)
> +{
> +   /* Page 679 of OpenGL 4.4 spec says:
> +    *    "Added BlitFramebuffer to commands affected by conditional rendering in
> +    *     section 10.10 (Bug 9562)."
> +    */
> +   if (!_mesa_check_conditional_render(ctx))
> +      return;
> +
> +   mask = intel_blit_framebuffer_with_blitter(ctx, readFb, drawFb,
> +                                              srcX0, srcY0, srcX1, srcY1,
> +                                              dstX0, dstY0, dstX1, dstY1,
> +                                              mask, filter);
> +   if (mask == 0x0)
> +      return;
> +
> +   mask = _mesa_meta_BlitFramebuffer(ctx, readFb, drawFb,
> +                                     srcX0, srcY0, srcX1, srcY1,
> +                                     dstX0, dstY0, dstX1, dstY1,
> +                                     mask, filter);
> +   if (mask == 0x0)
> +      return;
> +
> +   _swrast_BlitFramebuffer(ctx, readFb, drawFb,
> +                           srcX0, srcY0, srcX1, srcY1,
> +                           dstX0, dstY0, dstX1, dstY1,
> +                           mask, filter);
> +}
> +
> +/**
>   * Does the renderbuffer have hiz enabled?
>   */
>  bool
> @@ -1049,7 +1094,10 @@ intel_fbo_init(struct brw_context *brw)
>     dd->UnmapRenderbuffer = intel_unmap_renderbuffer;
>     dd->RenderTexture = intel_render_texture;
>     dd->ValidateFramebuffer = intel_validate_framebuffer;
> -   dd->BlitFramebuffer = intel_blit_framebuffer;
> +   if (brw->gen >= 6)
> +      dd->BlitFramebuffer = intel_blit_framebuffer;
> +   else
> +      dd->BlitFramebuffer = gen4_blit_framebuffer;
>     dd->EGLImageTargetRenderbufferStorage =
>        intel_image_target_renderbuffer_storage;
>  
> -- 
> 2.2.2
> 
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