[Mesa-stable] [PATCH 1/2] i965/skl: Add GT4 PCI IDs

Ben Widawsky benjamin.widawsky at intel.com
Fri Oct 23 10:54:36 PDT 2015


On Fri, Oct 23, 2015 at 10:37:29AM -0700, Ben Widawsky wrote:
> Like other gen8+ hardware, the hardware automatically scales up thread counts
> and URB sizes, so there is no need to do anything but add the PCI IDs.
> 
> FINISHME: This patch still needs testing before merge.
> 
> Cc: mesa-stable at lists.freedesktop.org
> Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
> ---
>  include/pci_ids/i965_pci_ids.h              | 5 ++++-
>  src/mesa/drivers/dri/i965/brw_device_info.c | 4 ++++
>  2 files changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h
> index 8a42599..7d23547 100644
> --- a/include/pci_ids/i965_pci_ids.h
> +++ b/include/pci_ids/i965_pci_ids.h
> @@ -122,8 +122,11 @@ CHIPSET(0x191D, skl_gt2, "Intel(R) Skylake WKS GT2")
>  CHIPSET(0x191E, skl_gt2, "Intel(R) Skylake ULX GT2")
>  CHIPSET(0x1921, skl_gt2, "Intel(R) Skylake ULT GT2F")
>  CHIPSET(0x1926, skl_gt3, "Intel(R) Skylake ULT GT3")
> -CHIPSET(0x192A, skl_gt3, "Intel(R) Skylake SRV GT3")
>  CHIPSET(0x192B, skl_gt3, "Intel(R) Skylake Halo GT3")

This should be removed in the next patch actually. I screwed up the rebase.

> +CHIPSET(0x1932, skl_gt4, "Intel(R) Skylake GT4")
> +CHIPSET(0x193A, skl_gt4, "Intel(R) Skylake GT4")
> +CHIPSET(0x193B, skl_gt4, "Intel(R) Skylake GT4")
> +CHIPSET(0x193D, skl_gt4, "Intel(R) Skylake GT4")
>  CHIPSET(0x22B0, chv,     "Intel(R) HD Graphics (Cherryview)")
>  CHIPSET(0x22B1, chv,     "Intel(R) HD Graphics (Cherryview)")
>  CHIPSET(0x22B2, chv,     "Intel(R) HD Graphics (Cherryview)")
> diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c b/src/mesa/drivers/dri/i965/brw_device_info.c
> index a6a3bb6..e7a016c 100644
> --- a/src/mesa/drivers/dri/i965/brw_device_info.c
> +++ b/src/mesa/drivers/dri/i965/brw_device_info.c
> @@ -335,6 +335,10 @@ static const struct brw_device_info brw_device_info_skl_gt3 = {
>     GEN9_FEATURES, .gt = 3,
>  };
>  
> +static const struct brw_device_info brw_device_info_skl_gt4 = {
> +   GEN9_FEATURES, .gt = 4,
> +};
> +
>  static const struct brw_device_info brw_device_info_bxt = {
>     GEN9_FEATURES,
>     .is_broxton = 1,
> -- 
> 2.6.1
> 

-- 
Ben Widawsky, Intel Open Source Technology Center


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