[Mesa-stable] New stable-branch 11.0 candidate pushed

[Mark Janes]

Can you please add this commit to the branch for 11.0.1?

commit 2ea16966ae66d4dd5c5dcb996d7996d9c734bbee
Author: Kristian Høgsberg Kristensen <krh at bitplanet.net>
Date:   Wed Sep 23 16:57:47 2015 -0700

    i965: Respect stride and subreg_offset for ATTR registers

It fixes a Braswell dEQP regression.

thanks,

Mark

Emil Velikov <emil.l.velikov at gmail.com> writes:

> Hello list,
>
> The candidate for the Mesa 11.0.1 is now available. Currently we have:
>  - 23 queued
>  - 29 nominated (outstanding)
>  - and 0 rejected/obsolete patches
>
> The present queue consists mostly of nouveau and i965 fixes, although we
> have the odd llvmpipe (big endian) and gbm bugfix.
>
>
> Note: we do have a sizeable list of nominated patches that have not been
> queued. Many of these are lacking review while the odd ones have gone
> stale despite the review and/or feedback given.
>
>
> Take a look at section "Mesa stable queue" for more information.
>
> Testing
> -------
> The following results are against piglit 4b6848c131c.
>
>
> Changes - classic i965(snb)
> ---------------------------
> None.
>
>
> Changes - swrast classic
> ------------------------
> None.
>
>
> Changes - gallium softpipe
> --------------------------
> None.
>
>
> Changes - gallium llvmpipe (LLVM 3.6.2)
> ---------------------------------------
> None.
>
>
> Testing reports/general approval
> --------------------------------
> Any testing reports (or general approval of the state of the branch)
> will be greatly appreciated.
>
>
> Trivial merge conflicts
> -----------------------
> None.
>
>
> The plan is to have 11.0.1 this Friday (25th of September) or shortly after.
>
> If you have any questions or comments that you would like to share
> before the release, please go ahead.
>
>
> Cheers,
> Emil
>
>
> Mesa stable queue
> -----------------
>
> Nominated (29)
> ==============
>
> Alejandro Piñeiro (2):
>       i965/vec4: check writemask when bailing out at register coalesce
>       i965/vec4: fill src_reg type using the constructor type parameter
>
> Anuj Phogat (1):
>       i965: Abort tiled_memcpy path for TexSubImage in case of transfer operations
>
> Ben Widawsky (2):
>       Revert "i965: Stop aux data compare preventing program binary re-use"
>       i965/skl: Use larger URB size where available.
>
> Benjamin Bellec (2):
>       gallium/hud: temperature is displayed with a percentage symbol, remove it
>       gallium/hud: display the Celsius temperature unit
>
> Boyan Ding (1):
>       i915: Add XRGB8888 format to intel_screen_make_configs
>
> Brian Paul (1):
>       configure: don't try to build gallium DRI drivers if --disable-dri is set
>
> Eduardo Lima Mitev (2):
>       mesa: Fix order of format+type and internal format checks for glTexImageXD ops
>       mesa: Move _mesa_base_tex_format() from teximage to glformats files
>
> Francisco Jerez (6):
>       i965: Don't tell the hardware about our UAV access.
>       mesa: Expose function to calculate whether a shader image unit is valid.
>       mesa: Skip redundant texture completeness checking during image validation.
>       i965: Use _mesa_is_image_unit_valid() instead of gl_image_unit::_Valid.
>       mesa: Get rid of texture-dependent image unit derived state.
>       i965/fs: Fix hang on IVB and VLV with image format mismatch.
>
> Ian Romanick (1):
>       meta: Handle array textures in scaled MSAA blits
>
> Jean-Sébastien Pédron (1):
>       ralloc: Use __attribute__((destructor)) instead of atexit(3)
>
> Kristian Høgsberg Kristensen (1):
>       i965: Respect stride and subreg_offset for ATTR registers
>
> Leo Liu (1):
>       radeon/vce: fix vui time_scale zero error
>
> Matthew Waters (1):
>       egl: rework handling EGL_CONTEXT_FLAGS
>
> Matt Turner (1)
>       glsl: Expose gl_MaxTess{Control, Evaluation}AtomicCounters.
>
> Rob Clark (1):
>       xa: add xa_surface_from_handle2
>
> Roland Scheidegger (1):
>       mesa: fix mipmap generation for immutable, compressed textures
>
> Tom Stellard (4):
>       clover: Call clBuildProgram() notification function when build completes v2
>       gallium/drivers: Add threadsafe wrappers for pipe_context v2
>       clover: Use threadsafe wrappers for pipe_context v2
>       clover: Properly initialize LLVM targets when linking with component libs
>
>
>
> Queued (23)
> ===========
>
> Antia Puentes (2):
>       i965/vec4: Fix saturation errors when coalescing registers
>       i965/vec4_nir: Load constants as integers
>
> Anuj Phogat (1):
>       meta: Abort meta pbo path if TexSubImage need signed unsigned conversion
>
> Emil Velikov (1):
>       docs: add sha256 checksums for 11.0.0
>
> Iago Toral Quiroga (1):
>       mesa: Fix GL_FRAMEBUFFER_ATTACHMENT_OBJECT_TYPE for default framebuffer.
>
> Ian Romanick (5):
>       t_dd_dmatmp: Make "count" actually be the count
>       t_dd_dmatmp: Clean up improper code formatting from previous patch
>       t_dd_dmatmp: Use '& 3' instead of '% 4' everywhere
>       t_dd_dmatmp: Pull out common 'count -= count & 3' code
>       t_dd_dmatmp: Use addition instead of subtraction in loop bounds
>
> Ilia Mirkin (6):
>       st/mesa: avoid integer overflows with buffers >= 512MB
>       nv50, nvc0: fix max texture buffer size to 128M elements
>       freedreno/a3xx: fix blending of L8 format
>       nv50,nvc0: detect underlying resource changes and update tic
>       nv50,nvc0: flush texture cache in presence of coherent bufs
>       radeonsi: load fmask ptr relative to the resources array
>
> Jason Ekstrand (2):
>       nir: Fix a bunch of ralloc parenting errors
>       i965/vec4: Don't reswizzle hardware registers
>
> Jeremy Huddleston (1):
>       configure.ac: Add support to enable read-only text segment on x86.
>
> Ray Strode (1):
>       gbm: convert gbm bo format to fourcc format on dma-buf import
>
> Tapani Pälli (2):
>       mesa: fix errors when reading depth with glReadPixels
>       i965: fix textureGrad for cubemaps
>
> Ulrich Weigand (1):
>       mesa: Fix texture compression on big-endian systems
>
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