[Mesa-stable] [PATCH] i965/hsw: Initialize SLM index in state register

[Ilia Mirkin]

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94081
Tested-by: Ilia Mirkin <imirkin at alum.mit.edu>

Seems to fix all the shared_var fails in dEQP here!

On Mon, Feb 22, 2016 at 2:35 PM, Jordan Justen
<jordan.l.justen at intel.com> wrote:
> For Haswell, we need to initialize the SLM index in the state
> register. This can be copied out of the CS header dword 0.
>
> Fixes piglit: arb_compute_shader/execution/shared-atomics.shader_test
>
> Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
> Cc: Ilia Mirkin <imirkin at alum.mit.edu>
> Cc: "11.2" <mesa-stable at lists.freedesktop.org>
> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp |  7 +++++++
>  src/mesa/drivers/dri/i965/brw_reg.h  | 16 ++++++++++++++++
>  2 files changed, 23 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index b506040..377c83d 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -5470,6 +5470,13 @@ fs_visitor::run_cs()
>     if (shader_time_index >= 0)
>        emit_shader_time_begin();
>
> +   if (devinfo->is_haswell && prog_data->total_shared > 0) {
> +      /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
> +      fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD));
> +      const fs_builder abld = bld.exec_all().group(1, 0);
> +      abld.SHR(suboffset(brw_sr0_reg(), 1), g0, brw_imm_d(16));
> +   }
> +
>     emit_nir_code();
>
>     if (failed)
> diff --git a/src/mesa/drivers/dri/i965/brw_reg.h b/src/mesa/drivers/dri/i965/brw_reg.h
> index a2a4a40..42a0a22 100644
> --- a/src/mesa/drivers/dri/i965/brw_reg.h
> +++ b/src/mesa/drivers/dri/i965/brw_reg.h
> @@ -737,6 +737,22 @@ brw_notification_reg(void)
>  }
>
>  static inline struct brw_reg
> +brw_sr0_reg(void)
> +{
> +   return brw_reg(BRW_ARCHITECTURE_REGISTER_FILE,
> +                  BRW_ARF_STATE,
> +                  0,
> +                  0,
> +                  0,
> +                  BRW_REGISTER_TYPE_UD,
> +                  BRW_VERTICAL_STRIDE_8,
> +                  BRW_WIDTH_8,
> +                  BRW_HORIZONTAL_STRIDE_1,
> +                  BRW_SWIZZLE_XYZW,
> +                  WRITEMASK_XYZW);
> +}
> +
> +static inline struct brw_reg
>  brw_acc_reg(unsigned width)
>  {
>     return brw_vecn_reg(width, BRW_ARCHITECTURE_REGISTER_FILE,
> --
> 2.7.0
>