[Mesa-stable] [Mesa-dev] [PATCH] i965/hsw: Initialize SLM index in state register

[Matt Turner]

On Mon, Feb 22, 2016 at 11:35 AM, Jordan Justen
<jordan.l.justen at intel.com> wrote:
> For Haswell, we need to initialize the SLM index in the state
> register. This can be copied out of the CS header dword 0.
>
> Fixes piglit: arb_compute_shader/execution/shared-atomics.shader_test
>
> Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
> Cc: Ilia Mirkin <imirkin at alum.mit.edu>
> Cc: "11.2" <mesa-stable at lists.freedesktop.org>
> ---
>  src/mesa/drivers/dri/i965/brw_fs.cpp |  7 +++++++
>  src/mesa/drivers/dri/i965/brw_reg.h  | 16 ++++++++++++++++
>  2 files changed, 23 insertions(+)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
> index b506040..377c83d 100644
> --- a/src/mesa/drivers/dri/i965/brw_fs.cpp
> +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
> @@ -5470,6 +5470,13 @@ fs_visitor::run_cs()
>     if (shader_time_index >= 0)
>        emit_shader_time_begin();
>
> +   if (devinfo->is_haswell && prog_data->total_shared > 0) {
> +      /* Move SLM index from g0.0[27:24] to sr0.1[11:8] */
> +      fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD));
> +      const fs_builder abld = bld.exec_all().group(1, 0);
> +      abld.SHR(suboffset(brw_sr0_reg(), 1), g0, brw_imm_d(16));

Nit: since the dst and src0 are UD, use brw_imm_ud(16).

The only other field in sr0.1 is "Fixed Function Thread ID" at 31:23.
I don't have any idea what overwriting that might do. Is that safe? Or
is the register simply uninitialized?

If that's safe, this patch is

Reviewed-by: Matt Turner <mattst88 at gmail.com>

But I don't think I can make that determination by myself.

Alternatively, if overwriting FFTID is bad, instead of emitting

   shr(1)  sr0.1:UD  g0.0:UD  16UD

you could write only the low word:

   mov(1)  sr0.2:UW  g0.1:UW

or maybe use an AND to ensure you're writing zeros to the MBZ bits of
the status register.