[Mesa-stable] [Mesa-dev] [PATCH] st/glsl_to_tgsi: fix dvec[34] loads from SSBO

[Marek Olšák]

Reviewed-by: Marek Olšák <marek.olsak at amd.com>

Marek

On Thu, Nov 3, 2016 at 11:04 AM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:
> From: Nicolai Hähnle <nicolai.haehnle at amd.com>
>
> When splitting up loads, we have to add 16 bytes to the offset for
> the high components, just like already happens for stores.
>
> Fixes arb_gpu_shader_fp64 at shader_storage@layout-std140-fp64-shader.
>
> Cc: 13.0 <mesa-stable at lists.freedesktop.org>
> ---
>  src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 10 ++++------
>  1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> index 5b53c40..882e959 100644
> --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
> @@ -767,55 +767,53 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op,
>
>        /*
>         * scan all the components in the dst writemask
>         * generate an instruction for each of them if required.
>         */
>        st_src_reg addr;
>        while (writemask) {
>
>           int i = u_bit_scan(&writemask);
>
> -         /* before emitting the instruction, see if we have to adjust store
> +         /* before emitting the instruction, see if we have to adjust load / store
>            * address */
> -         if (i > 1 && inst->op == TGSI_OPCODE_STORE &&
> +         if (i > 1 && (inst->op == TGSI_OPCODE_LOAD || inst->op == TGSI_OPCODE_STORE) &&
>               addr.file == PROGRAM_UNDEFINED) {
>              /* We have to advance the buffer address by 16 */
>              addr = get_temp(glsl_type::uint_type);
>              emit_asm(ir, TGSI_OPCODE_UADD, st_dst_reg(addr),
>                       inst->src[0], st_src_reg_for_int(16));
>           }
>
> -
>           /* first time use previous instruction */
>           if (dinst == NULL) {
>              dinst = inst;
>           } else {
>              /* create a new instructions for subsequent attempts */
>              dinst = new(mem_ctx) glsl_to_tgsi_instruction();
>              *dinst = *inst;
>              dinst->next = NULL;
>              dinst->prev = NULL;
>           }
>           this->instructions.push_tail(dinst);
>           dinst->is_64bit_expanded = true;
>
>           /* modify the destination if we are splitting */
>           for (j = 0; j < 2; j++) {
>              if (dst_is_64bit[j]) {
>                 dinst->dst[j].writemask = (i & 1) ? WRITEMASK_ZW : WRITEMASK_XY;
>                 dinst->dst[j].index = initial_dst_idx[j];
>                 if (i > 1) {
> -                  if (dinst->op == TGSI_OPCODE_STORE) {
> +                  if (dinst->op == TGSI_OPCODE_LOAD || dinst->op == TGSI_OPCODE_STORE)
>                       dinst->src[0] = addr;
> -                  } else {
> +                  if (dinst->op != TGSI_OPCODE_STORE)
>                       dinst->dst[j].index++;
> -                  }
>                 }
>              } else {
>                 /* if we aren't writing to a double, just get the bit of the initial writemask
>                    for this channel */
>                 dinst->dst[j].writemask = initial_dst_writemask[j] & (1 << i);
>              }
>           }
>
>           /* modify the src registers */
>           for (j = 0; j < 4; j++) {
> --
> 2.7.4
>
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