[Mesa-stable] [Mesa-dev] [PATCH 4/4] anv/cmd_buffer: Emit a CS stall before setting a CS pipeline

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>

On 22/11/16 04:26, Jason Ekstrand wrote:
> Cc: "13.0" <mesa-stable at lists.freedesktop.org>
> Cc: Jordan Justen <jordan.l.justen at intel.com>
> ---
>   src/intel/vulkan/genX_cmd_buffer.c | 14 +++++++++++++-
>   1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
> index eded1c9..6af2a18 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -1726,8 +1726,20 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer)
>   
>      genX(flush_pipeline_select_gpgpu)(cmd_buffer);
>   
> -   if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)
> +   if (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE) {
> +      /* From the Sky Lake PRM Vol 2a, MEDIA_VFE_STATE:
> +       *
> +       *    "A stalling PIPE_CONTROL is required before MEDIA_VFE_STATE unless
> +       *    the only bits that are changed are scoreboard related: Scoreboard
> +       *    Enable, Scoreboard Type, Scoreboard Mask, Scoreboard * Delta. For
> +       *    these scoreboard related states, a MEDIA_STATE_FLUSH is
> +       *    sufficient."
> +       */
> +      cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT;
> +      genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
> +
>         anv_batch_emit_batch(&cmd_buffer->batch, &pipeline->batch);
> +   }
>   
>      if (cmd_buffer->state.push_constants_dirty & VK_SHADER_STAGE_COMPUTE_BIT) {
>         struct anv_state push_state =