[Mesa-stable] [Mesa-dev] [PATCH] nvc0: do not break 3D state by pushing MS coordinates on Fermi
Samuel Pitoiset
samuel.pitoiset at gmail.com
Wed Oct 19 22:57:17 UTC 2016
On 10/20/2016 12:55 AM, Ilia Mirkin wrote:
> On Wed, Oct 19, 2016 at 6:46 PM, Samuel Pitoiset
> <samuel.pitoiset at gmail.com> wrote:
>> Long short story, 3D and CP are aliased on Fermi and initializing
>> compute after pushing the MS sample coordinate offsets seems to
>> corrupt 3D state for weird reasons.
>>
>> I still don't have the faintest clue what is going on, but
>> this seems to only affect Fermi generation. A possible fix
>> could be to use two different channels, one for 3D and one
>> for CP.
>>
>> This fixes a bunch of regressions pinpointed by piglit.
>>
>> Fixes: "nvc0: fix up image support for allowing multiple samples"
>> Cc: "12.0" <mesa-stable at lists.freedesktop.org>
>
> 13.0 I think, no? Or both?
Ah yeah, wrong copy&paste, I'm still in past. :-)
13.0 is enough because this has been introduced after 12.0 branchpoint.
>
>> Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
>
> Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
>
> The real deal is that compute messes up the bindings, and something
> down the line expects those bindings to be there.
Yeah, something like that.
>
>> ---
>>
>> This will require different piglit runs on both Fermi and Kepler+
>> to be sure I don't break anything else, but I'm quite confident.
>>
>> src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 87 +++++++++++++-------------
>> 1 file changed, 44 insertions(+), 43 deletions(-)
>>
>> diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
>> index cfa2f76..2cac3c7 100644
>> --- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
>> +++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
>> @@ -1002,49 +1002,6 @@ nvc0_screen_create(struct nouveau_device *dev)
>>
>> PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
>>
>> - for (i = 0; i < 5; ++i) {
>> - /* TIC and TSC entries for each unit (nve4+ only) */
>> - /* auxiliary constants (6 user clip planes, base instance id) */
>> - BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
>> - PUSH_DATA (push, NVC0_CB_AUX_SIZE);
>> - PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
>> - PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
>> - BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
>> - PUSH_DATA (push, (15 << 4) | 1);
>> - if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
>> - unsigned j;
>> - BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
>> - PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
>> - for (j = 0; j < 8; ++j)
>> - PUSH_DATA(push, j);
>> - } else {
>> - BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
>> - PUSH_DATA (push, 0x54);
>> - }
>> -
>> - /* MS sample coordinate offsets: these do not work with _ALT modes ! */
>> - BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
>> - PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
>> - PUSH_DATA (push, 0); /* 0 */
>> - PUSH_DATA (push, 0);
>> - PUSH_DATA (push, 1); /* 1 */
>> - PUSH_DATA (push, 0);
>> - PUSH_DATA (push, 0); /* 2 */
>> - PUSH_DATA (push, 1);
>> - PUSH_DATA (push, 1); /* 3 */
>> - PUSH_DATA (push, 1);
>> - PUSH_DATA (push, 2); /* 4 */
>> - PUSH_DATA (push, 0);
>> - PUSH_DATA (push, 3); /* 5 */
>> - PUSH_DATA (push, 0);
>> - PUSH_DATA (push, 2); /* 6 */
>> - PUSH_DATA (push, 1);
>> - PUSH_DATA (push, 3); /* 7 */
>> - PUSH_DATA (push, 1);
>> - }
>> - BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
>> - PUSH_DATA (push, 0);
>> -
>> /* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
>> BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
>> PUSH_DATA (push, 256);
>> @@ -1214,6 +1171,50 @@ nvc0_screen_create(struct nouveau_device *dev)
>> if (nvc0_screen_init_compute(screen))
>> goto fail;
>>
>> + /* XXX: Compute and 3D are somehow aliased on Fermi. */
>> + for (i = 0; i < 5; ++i) {
>> + /* TIC and TSC entries for each unit (nve4+ only) */
>> + /* auxiliary constants (6 user clip planes, base instance id) */
>> + BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
>> + PUSH_DATA (push, NVC0_CB_AUX_SIZE);
>> + PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
>> + PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
>> + BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
>> + PUSH_DATA (push, (15 << 4) | 1);
>> + if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
>> + unsigned j;
>> + BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
>> + PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
>> + for (j = 0; j < 8; ++j)
>> + PUSH_DATA(push, j);
>> + } else {
>> + BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
>> + PUSH_DATA (push, 0x54);
>> + }
>> +
>> + /* MS sample coordinate offsets: these do not work with _ALT modes ! */
>> + BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
>> + PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
>> + PUSH_DATA (push, 0); /* 0 */
>> + PUSH_DATA (push, 0);
>> + PUSH_DATA (push, 1); /* 1 */
>> + PUSH_DATA (push, 0);
>> + PUSH_DATA (push, 0); /* 2 */
>> + PUSH_DATA (push, 1);
>> + PUSH_DATA (push, 1); /* 3 */
>> + PUSH_DATA (push, 1);
>> + PUSH_DATA (push, 2); /* 4 */
>> + PUSH_DATA (push, 0);
>> + PUSH_DATA (push, 3); /* 5 */
>> + PUSH_DATA (push, 0);
>> + PUSH_DATA (push, 2); /* 6 */
>> + PUSH_DATA (push, 1);
>> + PUSH_DATA (push, 3); /* 7 */
>> + PUSH_DATA (push, 1);
>> + }
>> + BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
>> + PUSH_DATA (push, 0);
>> +
>> PUSH_KICK (push);
>>
>> screen->tic.entries = CALLOC(4096, sizeof(void *));
>> --
>> 2.10.0
>>
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