[Mesa-stable] [PATCH] intel: Correct the BDW surface state size

[Jason Ekstrand]

On Thu, Mar 9, 2017 at 8:18 PM, Kenneth Graunke <kenneth at whitecape.org>
wrote:

> On Thursday, March 9, 2017 3:35:15 PM PST Nanley Chery wrote:
> > The PRMs state that this packet is 16 DWORDS long. Ensure that the last
> > three DWORDS are zeroed as required by the hardware when allocating a
> > null surface state.
> >
> > Cc: <mesa-stable at lists.freedesktop.org>
> > Signed-off-by: Nanley Chery <nanley.g.chery at intel.com>
> > ---
> >  src/intel/isl/isl.c                            | 2 +-
> >  src/mesa/drivers/dri/i965/gen8_surface_state.c | 5 ++---
> >  2 files changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
> > index 6eb1e93efd..b4bdf2059a 100644
> > --- a/src/intel/isl/isl.c
> > +++ b/src/intel/isl/isl.c
> > @@ -56,7 +56,7 @@ static const struct {
> >     [5] = {24, 32,  4},
> >     [6] = {24, 32,  4},
> >     [7] = {32, 32,  4, 24},
> > -   [8] = {52, 64, 32, 40},
> > +   [8] = {64, 64, 32, 40},
> >     [9] = {64, 64, 32, 40},
> >  };
> >
> > diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> > index 501531d4ad..f868293217 100644
> > --- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
> > +++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
> > @@ -46,10 +46,9 @@ static uint32_t *
> >  gen8_allocate_surface_state(struct brw_context *brw,
> >                              uint32_t *out_offset, int index)
> >  {
> > -   int dwords = brw->gen >= 9 ? 16 : 13;
> >     uint32_t *surf = __brw_state_batch(brw, AUB_TRACE_SURFACE_STATE,
> > -                                      dwords * 4, 64, index,
> out_offset);
> > -   memset(surf, 0, dwords * 4);
> > +                                      64, 64, index, out_offset);
> > +   memset(surf, 0, 64);
> >     return surf;
> >  }
> >
> >
>
> Does this actually fix anything, or just use more batch space?
>

If you allocate more than one, it won't use any more batch space due to
alignments.
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