[Mesa-stable] [Mesa-dev] [PATCH 1/3] anv/cmd_buffer: Fix bad indentation

[Iago Toral]

All 3 patches are:

Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>

On Wed, 2017-03-15 at 11:58 -0700, Jason Ekstrand wrote:
> A bunch of code was indented in such a way that it looked like it
> went
> with the if statement above but it definitely didn't.
> 
> Cc: "17.0 13.0" <mesa-stable at lists.freedesktop.org>
> ---
>  src/intel/vulkan/genX_cmd_buffer.c | 49 +++++++++++++++++++---------
> ----------
>  1 file changed, 25 insertions(+), 24 deletions(-)
> 
> diff --git a/src/intel/vulkan/genX_cmd_buffer.c
> b/src/intel/vulkan/genX_cmd_buffer.c
> index 02dff44..2e95b98 100644
> --- a/src/intel/vulkan/genX_cmd_buffer.c
> +++ b/src/intel/vulkan/genX_cmd_buffer.c
> @@ -2040,32 +2040,33 @@ flush_pipeline_before_pipeline_select(struct
> anv_cmd_buffer *cmd_buffer,
>      */
>     if (pipeline == GPGPU)
>        anv_batch_emit(&cmd_buffer->batch,
> GENX(3DSTATE_CC_STATE_POINTERS), t);
> +
>  #elif GEN_GEN <= 7
> -      /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
> -       * PIPELINE_SELECT [DevBWR+]":
> -       *
> -       *   Project: DEVSNB+
> -       *
> -       *   Software must ensure all the write caches are flushed
> through a
> -       *   stalling PIPE_CONTROL command followed by another
> PIPE_CONTROL
> -       *   command to invalidate read only caches prior to
> programming
> -       *   MI_PIPELINE_SELECT command to change the Pipeline Select
> Mode.
> -       */
> -      anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
> -         pc.RenderTargetCacheFlushEnable  = true;
> -         pc.DepthCacheFlushEnable         = true;
> -         pc.DCFlushEnable                 = true;
> -         pc.PostSyncOperation             = NoWrite;
> -         pc.CommandStreamerStallEnable    = true;
> -      }
> +   /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
> +    * PIPELINE_SELECT [DevBWR+]":
> +    *
> +    *   Project: DEVSNB+
> +    *
> +    *   Software must ensure all the write caches are flushed
> through a
> +    *   stalling PIPE_CONTROL command followed by another
> PIPE_CONTROL
> +    *   command to invalidate read only caches prior to programming
> +    *   MI_PIPELINE_SELECT command to change the Pipeline Select
> Mode.
> +    */
> +   anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
> +      pc.RenderTargetCacheFlushEnable  = true;
> +      pc.DepthCacheFlushEnable         = true;
> +      pc.DCFlushEnable                 = true;
> +      pc.PostSyncOperation             = NoWrite;
> +      pc.CommandStreamerStallEnable    = true;
> +   }
>  
> -      anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
> -         pc.TextureCacheInvalidationEnable   = true;
> -         pc.ConstantCacheInvalidationEnable  = true;
> -         pc.StateCacheInvalidationEnable     = true;
> -         pc.InstructionCacheInvalidateEnable = true;
> -         pc.PostSyncOperation                = NoWrite;
> -      }
> +   anv_batch_emit(&cmd_buffer->batch, GENX(PIPE_CONTROL), pc) {
> +      pc.TextureCacheInvalidationEnable   = true;
> +      pc.ConstantCacheInvalidationEnable  = true;
> +      pc.StateCacheInvalidationEnable     = true;
> +      pc.InstructionCacheInvalidateEnable = true;
> +      pc.PostSyncOperation                = NoWrite;
> +   }
>  #endif
>  }
>