[Mesa-stable] [Mesa-dev] [PATCH 01/30] i965: Mark depth surfaces as needing a HiZ resolve after blitting

[Pohjolainen, Topi]

On Tue, May 30, 2017 at 10:11:26AM +0300, Pohjolainen, Topi wrote:
> 
> These both go to blitter engine which doesn't understand hiz. As the
> destination is resolved just before the blit, why do we need this?

Right, in terms of patch 14, this is the transition from Resolved to
Aux Invalid? Whereas after resolve aux and main surfaces are in sync, blit
engine causes them to get unsynchronized and aux needs hiz ambiguate cycle?

> 
> On Fri, May 26, 2017 at 04:30:05PM -0700, Jason Ekstrand wrote:
> > Cc: "17.0 17.1" <mesa-stable at lists.freedesktop.org>
> > ---
> >  src/mesa/drivers/dri/i965/intel_blit.c | 2 ++
> >  1 file changed, 2 insertions(+)
> > 
> > diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
> > index 2925fc2..b1e1eaa 100644
> > --- a/src/mesa/drivers/dri/i965/intel_blit.c
> > +++ b/src/mesa/drivers/dri/i965/intel_blit.c
> > @@ -329,6 +329,7 @@ intel_miptree_blit(struct brw_context *brw,
> >     intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
> >     intel_miptree_resolve_color(brw, src_mt, src_level, src_slice, 1, 0);
> >     intel_miptree_resolve_color(brw, dst_mt, dst_level, dst_slice, 1, 0);
> > +   intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_slice);
> >  
> >     if (src_flip)
> >        src_y = minify(src_mt->physical_height0, src_level - src_mt->first_level) - src_y - height;
> > @@ -387,6 +388,7 @@ intel_miptree_copy(struct brw_context *brw,
> >     intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_slice);
> >     intel_miptree_resolve_color(brw, src_mt, src_level, src_slice, 1, 0);
> >     intel_miptree_resolve_color(brw, dst_mt, dst_level, dst_slice, 1, 0);
> > +   intel_miptree_slice_set_needs_hiz_resolve(dst_mt, dst_level, dst_slice);
> >  
> >     uint32_t src_image_x, src_image_y;
> >     intel_miptree_get_image_offset(src_mt, src_level, src_slice,
> > -- 
> > 2.5.0.400.gff86faf
> > 
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