[Mesa-stable] [Mesa-dev] [PATCH] radeonsi/gfx9: always flush DB metadata on framebuffer changes
Marek Olšák
maraeo at gmail.com
Mon Sep 4 20:56:20 UTC 2017
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Marek
On Mon, Sep 4, 2017 at 2:16 PM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:
> From: Nicolai Hähnle <nicolai.haehnle at amd.com>
>
> This fixes GL45-CTS.shader_image_load_store.basic-glsl-earlyFragTests.
>
> Cc: mesa-stable at lists.freedesktop.org
> --
> FWIW, Vulkan also always flushes DB metadata on gfx9. Wait-for-idle
> is not required here.
> ---
> src/gallium/drivers/radeonsi/si_pipe.h | 4 ++--
> src/gallium/drivers/radeonsi/si_state.c | 11 ++++++++++-
> src/gallium/drivers/radeonsi/si_state_draw.c | 3 ++-
> 3 files changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
> index 386a6dc886d..b82ec7ef9f8 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.h
> +++ b/src/gallium/drivers/radeonsi/si_pipe.h
> @@ -54,23 +54,23 @@
> /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
> #define SI_CONTEXT_INV_VMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 2)
> /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
> #define SI_CONTEXT_INV_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 3)
> /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
> * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
> #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 4)
> /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
> * a CB or DB flush. */
> #define SI_CONTEXT_INV_L2_METADATA (R600_CONTEXT_PRIVATE_FLAG << 5)
> -/* gap */
> /* Framebuffer caches. */
> -#define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 7)
> +#define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
> +#define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 7)
> #define SI_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 8)
> /* Engine synchronization. */
> #define SI_CONTEXT_VS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 9)
> #define SI_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 10)
> #define SI_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
> #define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 12)
> #define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 13)
>
> #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
> #define SI_PREFETCH_LS (1 << 1)
> diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
> index 41b08f8de4f..365c1248b2f 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -2569,23 +2569,32 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
> sctx->framebuffer.CB_has_shader_readable_metadata);
>
> sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
>
> /* u_blitter doesn't invoke depth decompression when it does multiple
> * blits in a row, but the only case when it matters for DB is when
> * doing generate_mipmap. So here we flush DB manually between
> * individual generate_mipmap blits.
> * Note that lower mipmap levels aren't compressed.
> */
> - if (sctx->generate_mipmap_for_depth)
> + if (sctx->generate_mipmap_for_depth) {
> si_make_DB_shader_coherent(sctx, 1, false,
> sctx->framebuffer.DB_has_shader_readable_metadata);
> + } else if (sctx->b.chip_class == GFX9) {
> + /* It appears that DB metadata "leaks" in a sequence of:
> + * - depth clear
> + * - DCC decompress for shader image writes (with DB disabled)
> + * - render with DEPTH_BEFORE_SHADER=1
> + * Flushing DB metadata works around the problem.
> + */
> + sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
> + }
>
> /* Take the maximum of the old and new count. If the new count is lower,
> * dirtying is needed to disable the unbound colorbuffers.
> */
> sctx->framebuffer.dirty_cbufs |=
> (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
> sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
>
> si_dec_framebuffer_counters(&sctx->framebuffer.state);
> util_copy_framebuffer_state(&sctx->framebuffer.state, state);
> diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
> index 81751d2186e..7ee6cf88e88 100644
> --- a/src/gallium/drivers/radeonsi/si_state_draw.c
> +++ b/src/gallium/drivers/radeonsi/si_state_draw.c
> @@ -905,21 +905,22 @@ void si_emit_cache_flush(struct si_context *sctx)
> if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB)
> cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
> S_0085F0_DB_DEST_BASE_ENA(1);
> }
>
> if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
> /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
> radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
> }
> - if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
> + if (rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
> + SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
> /* Flush HTILE. SURFACE_SYNC will wait for idle. */
> radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
> radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
> }
>
> /* Wait for shader engines to go idle.
> * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
> * for everything including CB/DB cache flushes.
> */
> if (!flush_cb_db) {
> --
> 2.11.0
>
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