[Mesa-stable] [PATCH 4/4] ac/surface: match Z and stencil tile config

[Marek Olšák]

For the series:

Reviewed-by: Marek Olšák <marek.olsak at amd.com>

Marek

On Fri, Sep 8, 2017 at 7:16 PM, Nicolai Hähnle <nhaehnle at gmail.com> wrote:
> From: Nicolai Hähnle <nicolai.haehnle at amd.com>
>
> Fixes various piglit tests on Stoney, see the comment.
>
> Cc: mesa-stable at lists.freedesktop.org
> ---
>  src/amd/common/ac_surface.c | 49 ++++++++++++++++++++++++++++++++++++++-------
>  1 file changed, 42 insertions(+), 7 deletions(-)
>
> diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
> index 0c24116c6ac..21667adc66b 100644
> --- a/src/amd/common/ac_surface.c
> +++ b/src/amd/common/ac_surface.c
> @@ -581,29 +581,49 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
>                 info->chip_class >= VI &&
>                 !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
>                 !(surf->flags & RADEON_SURF_DISABLE_DCC) &&
>                 !compressed && AddrDccIn.numSamples <= 1 &&
>                 ((config->info.array_size == 1 && config->info.depth == 1) ||
>                  config->info.levels == 1);
>
>         AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
>         AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
>
> -       /* noStencil = 0 can result in a depth part that is incompatible with
> -        * mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
> -        * this case, we may end up setting stencil_adjusted).
> +       /* On CI/VI, the DB uses the same pitch and tile mode (except tilesplit)
> +        * for Z and stencil. This can cause a number of problems which we work
> +        * around here:
>          *
> -        * TODO: update addrlib to a newer version, remove this, and
> -        * use flags.matchStencilTileCfg = 1 as an alternative fix.
> +        * - a depth part that is incompatible with mipmapped texturing
> +        * - at least on Stoney, entirely incompatible Z/S aspects (e.g.
> +        *   incorrect tiling applied to the stencil part, stencil buffer
> +        *   memory accesses that go out of bounds) even without mipmapping
> +        *
> +        * Some piglit tests that are prone to different types of related
> +        * failures:
> +        *  ./bin/ext_framebuffer_multisample-upsample 2 stencil
> +        *  ./bin/framebuffer-blit-levels {draw,read} stencil
> +        *  ./bin/ext_framebuffer_multisample-unaligned-blit N {depth,stencil} {msaa,upsample,downsample}
> +        *  ./bin/fbo-depth-array fs-writes-{depth,stencil} / {depth,stencil}-{clear,layered-clear,draw}
> +        *  ./bin/depthstencil-render-miplevels 1024 d=s=z24_s8
>          */
> -       if (config->info.levels > 1)
> +       int stencil_tile_idx = -1;
> +
> +       if (AddrSurfInfoIn.flags.depth && !AddrSurfInfoIn.flags.noStencil &&
> +           (config->info.levels > 1 || info->family == CHIP_STONEY)) {
> +               /* Compute stencilTileIdx that is compatible with the (depth)
> +                * tileIdx. This degrades the depth surface if necessary to
> +                * ensure that a matching stencilTileIdx exists. */
> +               AddrSurfInfoIn.flags.matchStencilTileCfg = 1;
> +
> +               /* Keep the depth mip-tail compatible with texturing. */
>                 AddrSurfInfoIn.flags.noStencil = 1;
> +       }
>
>         /* Set preferred macrotile parameters. This is usually required
>          * for shared resources. This is for 2D tiling only. */
>         if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
>             surf->u.legacy.bankw && surf->u.legacy.bankh &&
>             surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
>                 assert(!(surf->flags & RADEON_SURF_FMASK));
>
>                 /* If any of these parameters are incorrect, the calculation
>                  * will fail. */
> @@ -675,31 +695,46 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
>                         if (r)
>                                 return r;
>
>                         if (level > 0)
>                                 continue;
>
>                         /* Check that we actually got a TC-compatible HTILE if
>                          * we requested it (only for level 0, since we're not
>                          * supporting HTILE on higher mip levels anyway). */
>                         assert(AddrSurfInfoOut.tcCompatible ||
> -                              !AddrSurfInfoIn.flags.tcCompatible);
> +                              !AddrSurfInfoIn.flags.tcCompatible ||
> +                              AddrSurfInfoIn.flags.matchStencilTileCfg);
> +
> +                       if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
> +                               if (!AddrSurfInfoOut.tcCompatible) {
> +                                       AddrSurfInfoIn.flags.tcCompatible = 0;
> +                                       surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
> +                               }
> +
> +                               AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
> +                               AddrSurfInfoIn.tileIndex = AddrSurfInfoOut.tileIndex;
> +                               stencil_tile_idx = AddrSurfInfoOut.stencilTileIdx;
> +
> +                               assert(stencil_tile_idx >= 0);
> +                       }
>
>                         r = gfx6_surface_settings(addrlib, info, config,
>                                                   &AddrSurfInfoOut, surf);
>                         if (r)
>                                 return r;
>                 }
>         }
>
>         /* Calculate texture layout information for stencil. */
>         if (surf->flags & RADEON_SURF_SBUFFER) {
> +               AddrSurfInfoIn.tileIndex = stencil_tile_idx;
>                 AddrSurfInfoIn.bpp = 8;
>                 AddrSurfInfoIn.flags.depth = 0;
>                 AddrSurfInfoIn.flags.stencil = 1;
>                 AddrSurfInfoIn.flags.tcCompatible = 0;
>                 /* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
>                 AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
>
>                 for (level = 0; level < config->info.levels; level++) {
>                         r = gfx6_compute_level(addrlib, config, surf, true, level, compressed,
>                                                &AddrSurfInfoIn, &AddrSurfInfoOut,
> --
> 2.11.0
>
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