[Mesa-stable] [PATCH 01/11] radeonsi: move current_rast_prim to r600_common_context

Nicolai Hähnle nhaehnle at gmail.com
Fri Sep 29 11:01:28 UTC 2017


From: Nicolai Hähnle <nicolai.haehnle at amd.com>

We'll use it in the scissors / clip / guardband state.

Cc: mesa-stable at lists.freedesktop.org
---
 src/gallium/drivers/radeon/r600_pipe_common.h   | 1 +
 src/gallium/drivers/radeonsi/si_pipe.h          | 1 -
 src/gallium/drivers/radeonsi/si_state_draw.c    | 8 ++++----
 src/gallium/drivers/radeonsi/si_state_shaders.c | 8 ++++----
 4 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index debedd402b4..f6ded92dc5b 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -592,20 +592,21 @@ struct r600_common_context {
 	struct r600_streamout		streamout;
 	struct r600_scissors		scissors;
 	struct r600_viewports		viewports;
 	bool				scissor_enabled;
 	bool				clip_halfz;
 	bool				vs_writes_viewport_index;
 	bool				vs_disables_clipping_viewport;
 
 	/* Additional context states. */
 	unsigned flags; /* flush flags */
+	enum pipe_prim_type		current_rast_prim; /* primitive type after TES, GS */
 
 	/* Queries. */
 	/* Maintain the list of active queries for pausing between IBs. */
 	int				num_occlusion_queries;
 	int				num_perfect_occlusion_queries;
 	struct list_head		active_queries;
 	unsigned			num_cs_dw_queries_suspend;
 	/* Misc stats. */
 	unsigned			num_draw_calls;
 	unsigned			num_decompress_calls;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 46c89e2f38a..08d47ea414e 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -402,21 +402,20 @@ struct si_context {
 	int			last_sh_base_reg;
 	int			last_primitive_restart_en;
 	int			last_restart_index;
 	int			last_gs_out_prim;
 	int			last_prim;
 	int			last_multi_vgt_param;
 	int			last_rast_prim;
 	unsigned		last_sc_line_stipple;
 	unsigned		current_vs_state;
 	unsigned		last_vs_state;
-	enum pipe_prim_type	current_rast_prim; /* primitive type after TES, GS */
 
 	/* Scratch buffer */
 	struct r600_atom	scratch_state;
 	struct r600_resource	*scratch_buffer;
 	unsigned		scratch_waves;
 	unsigned		spi_tmpring_size;
 
 	struct r600_resource	*compute_scratch_buffer;
 
 	/* Emitted derived tessellation state. */
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 0a672c503fd..e4f592c3845 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -524,21 +524,21 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
 			sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
 	}
 
 	return ia_multi_vgt_param;
 }
 
 /* rast_prim is the primitive type after GS. */
 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
 {
 	struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
-	enum pipe_prim_type rast_prim = sctx->current_rast_prim;
+	enum pipe_prim_type rast_prim = sctx->b.current_rast_prim;
 	struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
 
 	/* Skip this if not rendering lines. */
 	if (rast_prim != PIPE_PRIM_LINES &&
 	    rast_prim != PIPE_PRIM_LINE_LOOP &&
 	    rast_prim != PIPE_PRIM_LINE_STRIP &&
 	    rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
 	    rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
 		return;
 
@@ -574,21 +574,21 @@ static void si_emit_vs_state(struct si_context *sctx,
 		sctx->last_vs_state = sctx->current_vs_state;
 	}
 }
 
 static void si_emit_draw_registers(struct si_context *sctx,
 				   const struct pipe_draw_info *info,
 				   unsigned num_patches)
 {
 	struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
 	unsigned prim = si_conv_pipe_prim(info->mode);
-	unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
+	unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->b.current_rast_prim);
 	unsigned ia_multi_vgt_param;
 
 	ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
 
 	/* Draw state. */
 	if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
 		if (sctx->b.chip_class >= GFX9)
 			radeon_set_uconfig_reg_idx(cs, R_030960_IA_MULTI_VGT_PARAM, 4, ia_multi_vgt_param);
 		else if (sctx->b.chip_class >= CIK)
 			radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
@@ -1247,22 +1247,22 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
 	 * This must be done after si_decompress_textures, which can call
 	 * draw_vbo recursively, and before si_update_shaders, which uses
 	 * current_rast_prim for this draw_vbo call. */
 	if (sctx->gs_shader.cso)
 		rast_prim = sctx->gs_shader.cso->gs_output_prim;
 	else if (sctx->tes_shader.cso)
 		rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
 	else
 		rast_prim = info->mode;
 
-	if (rast_prim != sctx->current_rast_prim) {
-		sctx->current_rast_prim = rast_prim;
+	if (rast_prim != sctx->b.current_rast_prim) {
+		sctx->b.current_rast_prim = rast_prim;
 		sctx->do_update_shaders = true;
 	}
 
 	if (sctx->tes_shader.cso &&
 	    (sctx->b.family == CHIP_VEGA10 || sctx->b.family == CHIP_RAVEN)) {
 		/* Determine whether the LS VGPR fix should be applied.
 		 *
 		 * It is only required when num input CPs > num output CPs,
 		 * which cannot happen with the fixed function TCS. We should
 		 * also update this bit when switching from TCS to fixed
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 889cd8e7246..1146e5e3949 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1401,24 +1401,24 @@ static inline void si_shader_selector_key(struct pipe_context *ctx,
 		}
 
 		/* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
 		if (!key->part.ps.epilog.last_cbuf) {
 			key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
 			key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
 			key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
 		}
 
 		if (rs) {
-			bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
-					sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
-				       sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
-			bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
+			bool is_poly = (sctx->b.current_rast_prim >= PIPE_PRIM_TRIANGLES &&
+					sctx->b.current_rast_prim <= PIPE_PRIM_POLYGON) ||
+				       sctx->b.current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
+			bool is_line = !is_poly && sctx->b.current_rast_prim != PIPE_PRIM_POINTS;
 
 			key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
 			key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
 
 			if (sctx->queued.named.blend) {
 				key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
 							      rs->multisample_enable;
 			}
 
 			key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
-- 
2.11.0



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