[Mesa-stable] [Mesa-dev] [PATCH] intel/compiler: move nir_lower_bool_to_int32 before nir_lower_locals_to_regs
Juan A. Suarez Romero
jasuarez at igalia.com
Mon Dec 24 11:39:45 UTC 2018
On Fri, 2018-12-21 at 09:38 -0800, Kristian Høgsberg wrote:
> This regresses at least
> dEQP-GLES3.functional.shaders.functions.control_flow.return_in_loop_vertex
> on freedreno:
>
> Test case 'dEQP-GLES3.functional.shaders.functions.control_flow.return_in_loop_vertex'..
> deqp-gles3: ../../../mesa/src/compiler/nir/nir_lower_bool_to_int32.c:49:
> lower_alu_instr: Assertion `alu->dest.dest.is_ssa' failed.
>
Just to mention commit d6110d4d547 ("intel/compiler: move
nir_lower_bool_to_int32 before nir_lower_locals_to_regs") has not been picked
for 18.2 release branch.
J.A.
> Program received signal SIGABRT, Aborted.
> __libc_do_syscall () at ../sysdeps/unix/sysv/linux/arm/libc-do-syscall.S:47
> 47 ../sysdeps/unix/sysv/linux/arm/libc-do-syscall.S: No such file
> or directory.
> (gdb) bt
> #0 __libc_do_syscall () at ../sysdeps/unix/sysv/linux/arm/libc-do-syscall.S:47
> #1 0xf7cee18e in __libc_signal_restore_set (set=0xfffee2dc) at
> ../sysdeps/unix/sysv/linux/nptl-signals.h:80
> #2 __GI_raise (sig=sig at entry=6) at ../sysdeps/unix/sysv/linux/raise.c:48
> #3 0xf7ceef12 in __GI_abort () at abort.c:79
> #4 0xf7ce8e84 in __assert_fail_base (fmt=0xf7da3fdc "%s%s%s:%u:
> %s%sAssertion `%s' failed.\n%n", assertion=assertion at entry=0xffffffff
> <error: Cannot access memory at address 0xffffffff>, file=0xf7ae6d48
> "../../../mesa/src/compiler/nir/nir_lower_bool_to_int32.c",
> file at entry=0xf7c5d010 "", line=49, line at entry=4158390024,
> function=function at entry=0xf7b6be60 <__PRETTY_FUNCTION__.24316>
> "lower_alu_instr") at assert.c:92
> #5 0xf7ce8f22 in __GI___assert_fail (assertion=0xffffffff <error:
> Cannot access memory at address 0xffffffff>, file=0xf7c5d010 "",
> line=4158390024, line at entry=49, function=0xf7b6be60
> <__PRETTY_FUNCTION__.24316> "lower_alu_instr") at assert.c:101
> #6 0xf78f08ca in lower_alu_instr (alu=0xf7dbff08 <lock>) at
> ../../../mesa/src/compiler/nir/nir_lower_bool_to_int32.c:49
> #7 nir_lower_bool_to_int32_impl (impl=0xf8e378) at
> ../../../mesa/src/compiler/nir/nir_lower_bool_to_int32.c:114
> #8 nir_lower_bool_to_int32 (shader=<optimized out>) at
> ../../../mesa/src/compiler/nir/nir_lower_bool_to_int32.c:157
> #9 0xf7a97584 in ir3_context_init (compiler=0xbe31c0,
> so=so at entry=0xf97378) at
> ../../../mesa/src/freedreno/ir3/ir3_context.c:80
> #10 0xf7a95f58 in ir3_compile_shader_nir (compiler=<optimized out>,
> so=so at entry=0xf97378) at
> ../../../mesa/src/freedreno/ir3/ir3_compiler_nir.c:2994
> #11 0xf7aa1adc in create_variant (shader=shader at entry=0xf9fe60,
> key=key at entry=0xfffee764, binning_pass=binning_pass at entry=true) at
> ../../../mesa/src/freedreno/ir3/ir3_shader.c:182
> #12 0xf7aa1d9c in ir3_shader_get_variant (shader=0xf9fe60,
> key=key at entry=0xfffee764, binning_pass=<optimized out>,
> created=0xfffee743, created at entry=0xfffee723) at
> ../../../mesa/src/freedreno/ir3/ir3_shader.c:233
> #13 0xf7a88068 in ir3_shader_variant (shader=<optimized out>, key=...,
> binning_pass=binning_pass at entry=true, debug=debug at entry=0xc9a794) at
> ../../../../../mesa/src/gallium/drivers/freedreno/ir3/ir3_gallium.c:86
> #14 0xf7a87a74 in ir3_cache_lookup (cache=0xc89520,
> key=key at entry=0xfffee844, debug=debug at entry=0xc9a794) at
> ../../../../../mesa/src/gallium/drivers/freedreno/ir3/ir3_cache.c:96
> #15 0xf7a7ad6e in fd6_emit_get_prog (emit=0xfffee838) at
> ../../../../../mesa/src/gallium/drivers/freedreno/a6xx/fd6_emit.h:103
> #16 fd6_draw_vbo (ctx=0xc95ca0, info=0xfffeea70, index_offset=80) at
> ../../../../../mesa/src/gallium/drivers/freedreno/a6xx/fd6_draw.c:186
> #17 0xf7a4551a in fd_draw_vbo (pctx=<optimized out>, info=0xfffeea70)
> at ../../../../../mesa/src/gallium/drivers/freedreno/freedreno_draw.c:291
> #18 0xf79f8802 in u_vbuf_draw_vbo (mgr=<optimized out>,
> info=<optimized out>) at
> ../../../../mesa/src/gallium/auxiliary/util/u_vbuf.c:1449
> #19 0xf77d2f42 in st_draw_vbo (ctx=<optimized out>, prims=0xfffeed54,
> nr_prims=<optimized out>, ib=0xfffeed44, index_bounds_valid=0 '\000',
> min_index=0, max_index=3, tfb_vertcount=0x0, stream=0, indirect=0x0)
> at ../../../mesa/src/mesa/state_tracker/st_draw.c:268
> #20 0xf766b338 in _mesa_validated_drawrangeelements (ctx=0xca3e00,
> mode=mode at entry=4, index_bounds_valid=<optimized out>,
> start=<optimized out>, end=end at entry=4294967295, count=count at entry=6,
> type=type at entry=5123, indices=indices at entry=0xac3d60, basevertex=0,
> numInstances=numInstances at entry=1, baseInstance=0) at
> ../../../mesa/src/mesa/main/draw.c:849
> #21 0xf766c36a in _mesa_validated_drawrangeelements (baseInstance=0,
> numInstances=1, basevertex=0, indices=0xac3d60, type=5123, count=6,
> end=4294967295, start=0, index_bounds_valid=0 '\000', mode=4,
> ctx=<optimized out>) at ../../../mesa/src/mesa/main/draw.c:768
> #22 _mesa_DrawElements (mode=4, count=6, type=5123, indices=0xac3d60)
> at ../../../mesa/src/mesa/main/draw.c:1003
> #23 0x008f4e94 in _start ()
>
> Kristian
>
> On Wed, Dec 19, 2018 at 12:16 AM Iago Toral Quiroga <itoral at igalia.com> wrote:
> > The former expects to see SSA-only things, but the latter injects registers.
> >
> > The assertions in the lowering where not seeing this because they asserted
> > on the bit_size values only, not on the is_ssa field, so add that assertion
> > too.
> >
> > Fixes: 11dc1307794e "nir: Add a bool to int32 lowering pass"
> > CC: mesa-stable at lists.freedesktop.org
> > ---
> > src/compiler/nir/nir_lower_bool_to_int32.c | 2 ++
> > src/intel/compiler/brw_nir.c | 4 ++--
> > 2 files changed, 4 insertions(+), 2 deletions(-)
> >
> > diff --git a/src/compiler/nir/nir_lower_bool_to_int32.c b/src/compiler/nir/nir_lower_bool_to_int32.c
> > index 064b27b9025..fdd2f55175d 100644
> > --- a/src/compiler/nir/nir_lower_bool_to_int32.c
> > +++ b/src/compiler/nir/nir_lower_bool_to_int32.c
> > @@ -46,6 +46,8 @@ lower_alu_instr(nir_alu_instr *alu)
> > {
> > const nir_op_info *op_info = &nir_op_infos[alu->op];
> >
> > + assert(alu->dest.dest.is_ssa);
> > +
> > switch (alu->op) {
> > case nir_op_imov:
> > case nir_op_vec2:
> > diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
> > index ab88a5f1fc7..4fdc98b6cf4 100644
> > --- a/src/intel/compiler/brw_nir.c
> > +++ b/src/intel/compiler/brw_nir.c
> > @@ -832,6 +832,8 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
> > OPT(nir_opt_dce);
> > OPT(nir_opt_move_comparisons);
> >
> > + OPT(nir_lower_bool_to_int32);
> > +
> > OPT(nir_lower_locals_to_regs);
> >
> > if (unlikely(debug_enabled)) {
> > @@ -846,8 +848,6 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
> > nir_print_shader(nir, stderr);
> > }
> >
> > - OPT(nir_lower_bool_to_int32);
> > -
> > OPT(nir_convert_from_ssa, true);
> >
> > if (!is_scalar) {
> > --
> > 2.17.1
> >
> > _______________________________________________
> > mesa-dev mailing list
> > mesa-dev at lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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