[Mesa-stable] [Mesa-dev] [PATCH 02/17] i965/miptree: Zero-initialize CCS_D buffers

[Nanley Chery]

On Tue, May 22, 2018 at 01:09:18PM +0200, Juan A. Suarez Romero wrote:
> On Thu, 2018-05-03 at 14:22 -0700, Nanley Chery wrote:
> > On Thu, May 03, 2018 at 12:40:49PM -0700, Jason Ekstrand wrote:
> > > Good catch. Rb
> > > 
> > 
> > Thanks!
> > 
> > > On May 3, 2018 12:04:59 Nanley Chery <nanleychery at gmail.com> wrote:
> > > 
> > > > Before this patch, the aux_state was actually AUX_INVALID because the BO
> > > > was never defined. This was fine on single slice miptrees because we
> > > > would fast-clear the resource right after creation. For multi-slice
> > > > miptrees on SKL+ however, this results in undefined behavior when
> > > > accessing a non-base slice. Here's a specific example:
> > > > 
> > > > 1) Fast clear level 0
> > > >   * Undefined CCS_D buffer allocated in "PASS_THROUGH" state.
> > > >   * Level 0 transitions to the CLEAR state.
> > > > 2) Render to level 1
> > > >   * Level 1 may have a 2-bit pattern of 2's.
> > > >   * Rendering with a 2 in the CCS is undefined.
> > > > 
> > > > Cc: <mesa-stable at lists.freedesktop.org>
> 
> 
> This patch does not apply cleanly in 18.0, so I've resolved the trivial
> conflict:
> 
> 
> https://github.com/Igalia/release-mesa/commit/3b7134c5350df5fcc04b71d9598154bbc6
> 451256
> 

Looks good to me. Thanks for getting this into 18.0.

-Nanley

> 	J.A.
> 
> 
> > > > ---
> > > > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 ++++------
> > > > 1 file changed, 4 insertions(+), 6 deletions(-)
> > > > 
> > > > diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > > b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > > index 377efae32c9..182a896e23a 100644
> > > > --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > > +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
> > > > @@ -1806,13 +1806,11 @@ intel_miptree_alloc_ccs(struct brw_context *brw,
> > > >     * A CCS value of 0 indicates that the corresponding block is in the
> > > >     * pass-through state which is what we want.
> > > >     *
> > > > -    * For CCS_D, on the other hand, we don't care as we're about to perform a
> > > > -    * fast-clear operation.  In that case, being hot in caches more useful.
> > > > +    * For CCS_D, do the same thing. On gen9+, this avoids having any undefined
> > > > +    * bits in the aux buffer.
> > > >     */
> > > > -   const uint32_t alloc_flags = mt->aux_usage == ISL_AUX_USAGE_CCS_E ?
> > > > -                                BO_ALLOC_ZEROED : BO_ALLOC_BUSY;
> > > > -   mt->aux_buf = intel_alloc_aux_buffer(brw, "ccs-miptree",
> > > > -                                        &temp_ccs_surf, alloc_flags, mt);
> > > > +   mt->aux_buf = intel_alloc_aux_buffer(brw, "ccs-miptree", &temp_ccs_surf,
> > > > +                                        BO_ALLOC_ZEROED, mt);
> > > >    if (!mt->aux_buf) {
> > > >       free(aux_state);
> > > >       return false;
> > > > --
> > > > 2.16.2
> > > > 
> > > > _______________________________________________
> > > > mesa-dev mailing list
> > > > mesa-dev at lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/mesa-dev
> > > 
> > > 
> > > 
> > 
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