[Mesa-stable] [PATCH 21/53] intel/fs: Properly copy default flag reg for 3src instrucitons

[Jason Ekstrand]

Prior to gen8, the flag reg and subreg numbers are in different
locations on 3src instructions than on smaller instructions.  In order
for brw_set_default_flag_reg to work properly, we need to copy the value
out of the 2src location and write it into the 3src location as part of
brw_alu3.

Cc: mesa-stable at lists.freedesktop.org
---
 src/intel/compiler/brw_eu_emit.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index 3d65f29..294bea0 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -824,6 +824,18 @@ brw_alu3(struct brw_codegen *p, unsigned opcode, struct brw_reg dest,
              dest.type == BRW_REGISTER_TYPE_DF ||
              dest.type == BRW_REGISTER_TYPE_D  ||
              dest.type == BRW_REGISTER_TYPE_UD);
+
+      /* Flag registers are in a different spot on 3src instructions so we
+       * need to move the value if we want brw_set_default_flag_reg to work
+       * properly.
+       */
+      unsigned flag_reg_nr =
+         devinfo->gen >= 7 ? brw_inst_flag_reg_nr(devinfo, inst) : 0;
+      unsigned flag_subreg_nr = brw_inst_flag_subreg_nr(devinfo, inst);
+      if (devinfo->gen >= 7)
+         brw_inst_set_3src_a16_flag_reg_nr(devinfo, inst, flag_reg_nr);
+      brw_inst_set_3src_a16_flag_subreg_nr(devinfo, inst, flag_subreg_nr);
+
       if (devinfo->gen == 6) {
          brw_inst_set_3src_a16_dst_reg_file(devinfo, inst,
                                             dest.file == BRW_MESSAGE_REGISTER_FILE);
-- 
2.5.0.400.gff86faf