[Mesa-stable] [PATCH 3/4] intel/eu: Set flag [sub]register number differently for 3src

[Jason Ekstrand]

Prior to gen8, the flag [sub]register number is in a different spot on
3src instructions than on other instructions.  Starting with Broadwell,
they made it consistent.  This commit fixes bugs that occur when a
conditional modifier gets propagated into a 3src instruction such as a
MAD.

Cc: mesa-stable at lists.freedesktop.org
---
 src/intel/compiler/brw_eu_emit.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index b2bce0e..0dfe26a 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -701,9 +701,16 @@ brw_inst_set_state(const struct gen_device_info *devinfo,
    brw_inst_set_pred_control(devinfo, insn, state->predicate);
    brw_inst_set_pred_inv(devinfo, insn, state->pred_inv);
 
-   brw_inst_set_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2);
-   if (devinfo->gen >= 7)
-      brw_inst_set_flag_reg_nr(devinfo, insn, state->flag_subreg / 2);
+   if (is_3src(devinfo, brw_inst_opcode(devinfo, insn)) &&
+       state->access_mode == BRW_ALIGN_16) {
+      brw_inst_set_3src_a16_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2);
+      if (devinfo->gen >= 7)
+         brw_inst_set_3src_a16_flag_reg_nr(devinfo, insn, state->flag_subreg / 2);
+   } else {
+      brw_inst_set_flag_subreg_nr(devinfo, insn, state->flag_subreg % 2);
+      if (devinfo->gen >= 7)
+         brw_inst_set_flag_reg_nr(devinfo, insn, state->flag_subreg / 2);
+   }
 
    if (devinfo->gen >= 6)
       brw_inst_set_acc_wr_control(devinfo, insn, state->acc_wr_control);
-- 
2.5.0.400.gff86faf