<div dir="ltr">drp... This should have been two patches... I'll resend<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Fri, Nov 25, 2016 at 10:13 PM, Jason Ekstrand <span dir="ltr"><<a href="mailto:jason@jlekstrand.net" target="_blank">jason@jlekstrand.net</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">The 1-D special case doesn't actually apply to depth or HiZ. I discovered<br>
this while converting BLORP over to genxml and ISL. The reason is that the<br>
1-D special case only applies to the new Sky Lake 1-D layout which is only<br>
used for LINEAR 1-D images. For tiled 1-D images, such as depth buffers,<br>
the old gen4 2-D layout is used and the QPitch should be in rows.<br>
<br>
Cc: Nanley Chery <<a href="mailto:nanley.g.chery@intel.com">nanley.g.chery@intel.com</a>><br>
Cc: "13.0" <<a href="mailto:mesa-stable@lists.freedesktop.org">mesa-stable@lists.<wbr>freedesktop.org</a>><br>
---<br>
src/intel/isl/isl.h | 15 ++++++++++++++-<br>
src/intel/isl/isl_surface_<wbr>state.c | 12 ++++--------<br>
src/intel/vulkan/genX_cmd_<wbr>buffer.c | 9 ++++++---<br>
3 files changed, 24 insertions(+), 12 deletions(-)<br>
<br>
diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h<br>
index 07368f9..427724a 100644<br>
--- a/src/intel/isl/isl.h<br>
+++ b/src/intel/isl/isl.h<br>
@@ -1336,7 +1336,7 @@ isl_surf_get_image_alignment_<wbr>sa(const struct isl_surf *surf)<br>
* Pitch between vertically adjacent surface elements, in bytes.<br>
*/<br>
static inline uint32_t<br>
-isl_surf_get_row_pitch(const struct isl_surf *surf)<br>
+isl_surf_get_row_pitch_B(<wbr>const struct isl_surf *surf)<br>
{<br>
return surf->row_pitch;<br>
}<br>
@@ -1354,6 +1354,19 @@ isl_surf_get_row_pitch_el(<wbr>const struct isl_surf *surf)<br>
}<br>
<br>
/**<br>
+ * Pitch between vertically adjacent tiles, in units of tiles.<br>
+ */<br>
+static inline uint32_t<br>
+isl_surf_get_row_pitch_tl(<wbr>const struct isl_device *dev,<br>
+ const struct isl_surf *surf)<br>
+{<br>
+ assert(surf->tiling != ISL_TILING_LINEAR);<br>
+ struct isl_tile_info tile_info;<br>
+ isl_surf_get_tile_info(dev, surf, &tile_info);<br>
+ return surf->row_pitch / tile_info.phys_extent_B.width;<br>
+}<br>
+<br>
+/**<br>
* Pitch between physical array slices, in rows of surface elements.<br>
*/<br>
static inline uint32_t<br>
diff --git a/src/intel/isl/isl_surface_<wbr>state.c b/src/intel/isl/isl_surface_<wbr>state.c<br>
index 3bb0abd..27468b3 100644<br>
--- a/src/intel/isl/isl_surface_<wbr>state.c<br>
+++ b/src/intel/isl/isl_surface_<wbr>state.c<br>
@@ -405,7 +405,7 @@ isl_genX(surf_fill_state_s)(<wbr>const struct isl_device *dev, void *state,<br>
/* For gen9 1-D textures, surface pitch is ignored */<br>
s.SurfacePitch = 0;<br>
} else {<br>
- s.SurfacePitch = info->surf->row_pitch - 1;<br>
+ s.SurfacePitch = isl_surf_get_row_pitch_B(info-<wbr>>surf) - 1;<br>
}<br>
<br>
#if GEN_GEN >= 8<br>
@@ -503,14 +503,10 @@ isl_genX(surf_fill_state_s)(<wbr>const struct isl_device *dev, void *state,<br>
<br>
#if GEN_GEN >= 7<br>
if (info->aux_surf && info->aux_usage != ISL_AUX_USAGE_NONE) {<br>
- struct isl_tile_info tile_info;<br>
- isl_surf_get_tile_info(dev, info->aux_surf, &tile_info);<br>
- uint32_t pitch_in_tiles =<br>
- info->aux_surf->row_pitch / tile_info.phys_extent_B.width;<br>
-<br>
#if GEN_GEN >= 8<br>
assert(GEN_GEN >= 9 || info->aux_usage != ISL_AUX_USAGE_CCS_E);<br>
- s.AuxiliarySurfacePitch = pitch_in_tiles - 1;<br>
+ s.AuxiliarySurfacePitch =<br>
+ isl_surf_get_row_pitch_tl(dev, info->aux_surf) - 1;<br>
/* Auxiliary surfaces in ISL have compressed formats but the hardware<br>
* doesn't expect our definition of the compression, it expects qpitch<br>
* in units of samples on the main surface.<br>
@@ -523,7 +519,7 @@ isl_genX(surf_fill_state_s)(<wbr>const struct isl_device *dev, void *state,<br>
assert(info->aux_usage == ISL_AUX_USAGE_MCS ||<br>
info->aux_usage == ISL_AUX_USAGE_CCS_D);<br>
s.MCSBaseAddress = info->aux_address,<br>
- s.MCSSurfacePitch = pitch_in_tiles - 1;<br>
+ s.MCSSurfacePitch = isl_surf_get_row_pitch_tl(dev, info->aux_surf) - 1;<br>
s.MCSEnable = true;<br>
#endif<br>
}<br>
diff --git a/src/intel/vulkan/genX_cmd_<wbr>buffer.c b/src/intel/vulkan/genX_cmd_<wbr>buffer.c<br>
index a965cd6..2ef1745 100644<br>
--- a/src/intel/vulkan/genX_cmd_<wbr>buffer.c<br>
+++ b/src/intel/vulkan/genX_cmd_<wbr>buffer.c<br>
@@ -2130,11 +2130,14 @@ cmd_buffer_emit_depth_stencil(<wbr>struct anv_cmd_buffer *cmd_buffer)<br>
* - SURFTYPE_1D: distance in pixels between array slices<br>
* - SURFTYPE_2D/CUBE: distance in rows between array slices<br>
* - SURFTYPE_3D: distance in rows between R - slices<br>
+ *<br>
+ * Unfortunately, the docs aren't 100% accurate here. They fail to<br>
+ * mention that the 1-D rule only applies to linear 1-D images.<br>
+ * Since depth and HiZ buffers are always tiled, we use the 2-D rule<br>
+ * in the 1-D case.<br>
*/<br>
hdb.SurfaceQPitch =<br>
- image->aux_surface.isl.dim == ISL_SURF_DIM_1D ?<br>
- isl_surf_get_array_pitch_el(&<wbr>image->aux_surface.isl) >> 2 :<br>
- isl_surf_get_array_pitch_el_<wbr>rows(&image->aux_surface.isl) >> 2;<br>
+ isl_surf_get_array_pitch_el_<wbr>rows(&image->aux_surface.isl) >> 2;<br>
#endif<br>
}<br>
} else {<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.5.0.400.gff86faf<br>
<br>
</font></span></blockquote></div><br></div>