[Nouveau] [PATCH 2/2] drm/nv50: Improve PGRAPH interrupt handling.

[Marcin Kościelnicki]

> Register 0x402000 is used by nv40 to acknowledge DMA_VTX_PROTECTION
> (see code), which is caused by out-of-bounds indices in index buffers
> (and perhaps other vertex-related stuff): maybe it does something
> similar on nv50.

No. Pre-NV50 traps are totally different than NV50. Trap registers like 400200 
take 0xc0000000 to ACK, not writing back the same value. Also, vertex fetches 
cause trap at 0x400c04 which we already handle, and index buffers are handled 
by PFIFO [better PFIFO error handling would be much appreciated, but that's 
best left for another patch].

0x402000 is pretty much certain to work just like 0x400c04, 0x401800, 
0x405018, 0x406800 registers, just apply to a different subunit of PGRAPH 
accessing memory. Since DMA slots mostly have a many-to-one relationship to 
the trap-reporting PGRAPH subunits [with exception of m2mf's DMA_NOTIFY which 
is accessed by both DISPATCH for normal notifies and M2MF for buffer 
notifies], it's likely that it corresponds to that last unknown DMA slot on 
NV50TCL [as I mentioned in code]. So to RE it, you'd first need to figure out 
the NV50TCL bits... does anyone know of any type of memory buffer that GPUs 
use and isn't yet covered by what's in renouveau.xml?

> Also, wouldn't some of this apply to pre-nv50 too? Or is that already
> implemented?

Mostly no, since the interrupts are much different... the major fault of 
previous code was assuming that nv50 is just a bigger nv40 and trying to fit 
stuff forcefully by faking nsource/nstatus. Also, pre-NV50 DISPATCH unit 
either doesn't exist, or is very different.

Two things that pre-NV50 could get that I know of are MISSING_HW interrupt 
[0x10, happens for some methods in 0x200-0x20c range on some objects] and 
SINGLE_STEP interrupt [not that important, since nouveau gives you no way yet 
to enable single stepping sans manually poking PGRAPH_DEBUG_3].

I fear that pre-NV50 simply needs its own long RE session to make nouveau 
decode interrupts in as much detail as NV50. I'd recommend taking a look at 
rules.xml, it should be very relevant at least for NV10-NV30, if not also 
NV40.

Oh, and a nice thing to do would be decoding 0x400700 bits and displaying them 
along with the error. Maybe something useful information could come out of it.

Marcin Kościelnicki