[Nouveau] [PATCH 5/7] drm/nv3x/mpeg: fix bits being masked to indicate vram/agp access

[Ilia Mirkin]

In the process, fixes the VRAM check for DMA_IMAGE.

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
 drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
index c190043..30dc047 100644
--- a/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
+++ b/drivers/gpu/drm/nouveau/core/engine/mpeg/nv31.c
@@ -82,6 +82,8 @@ nv31_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len)
 	u32 dma2 = nv_ro32(imem, inst + 8);
 	u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
 	u32 size = dma1 + 1;
+	u32 mem_target = dma0 & 0x00030000;
+	bool nv3x = nv_device(priv)->chipset < 0x40;
 
 	/* only allow linear DMA objects */
 	if (!(dma0 & 0x00002000))
@@ -89,18 +91,24 @@ nv31_mpeg_mthd_dma(struct nouveau_object *object, u32 mthd, void *arg, u32 len)
 
 	if (mthd == 0x0190) {
 		/* DMA_CMD */
-		nv_mask(priv, 0x00b300, 0x00030000, (dma0 & 0x00030000));
+		if (nv3x)
+			nv_mask(priv, 0x00b300, 0x00010000, mem_target ? 0x00010000 : 0);
+		else
+			nv_mask(priv, 0x00b300, 0x00030000, mem_target);
 		nv_wr32(priv, 0x00b334, base);
 		nv_wr32(priv, 0x00b324, size);
 	} else
 	if (mthd == 0x01a0) {
 		/* DMA_DATA */
-		nv_mask(priv, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
+		if (nv3x)
+			nv_mask(priv, 0x00b300, 0x00020000, mem_target ? 0x00020000 : 0);
+		else
+			nv_mask(priv, 0x00b300, 0x000c0000, mem_target << 2);
 		nv_wr32(priv, 0x00b360, base);
 		nv_wr32(priv, 0x00b364, size);
 	} else {
 		/* DMA_IMAGE, VRAM only */
-		if (dma0 & 0x000c0000)
+		if (mem_target)
 			return -EINVAL;
 
 		nv_wr32(priv, 0x00b370, base);
-- 
1.8.1.5