[Nouveau] [PATCH envytools] demmio: Add decoding of some MEM_TIMINGS registers for NVC0.

[Christian Costa]

Le 26/08/2014 00:30, Martin Peres a écrit :
> On 25/08/2014 20:58, Christian Costa wrote:
>> ---
>>   rnndb/memory/nvc0_pbfb.xml | 37 ++++++++++++++++++++++++++++++++++---
>>   1 file changed, 34 insertions(+), 3 deletions(-)
>>
>> diff --git a/rnndb/memory/nvc0_pbfb.xml b/rnndb/memory/nvc0_pbfb.xml
>> index 500cea9..e006dbe 100644
>> --- a/rnndb/memory/nvc0_pbfb.xml
>> +++ b/rnndb/memory/nvc0_pbfb.xml
>> @@ -49,23 +49,54 @@
>>               Most bitfields are unknown.
>>               </doc>
>>           <bitfield high="7" low="0" name="RP">
>> -            <doc> RAS# precharge. </doc>
>> +            <doc> RAS# Precharge. </doc>
>>           </bitfield>
>>           <bitfield high="15" low="8" name="RAS">
>> -            <doc>Activate to precharge delay. </doc>
>> +            <doc> Activate to precharge delay. </doc>
>>           </bitfield>
>>           <bitfield high="23" low="16" name="RFC">
>>               <doc> Refresh to activate delay. </doc>
>>           </bitfield>
>>           <bitfield high="31" low="24" name="RC">
>> -            <doc> Row cycle time. </doc>
>> +            <doc> Row Cycle time. </doc>
>> +        </bitfield>
>> +    </reg32>
>> +
>> +    <reg32 offset="0x290" name="MEM_TIMINGS_0" variants="NVC0-">
>> +        <doc> This, and the next 6 regs, are all related to memtimings.
>> +            A good place to read might be 
>> http://www.tweakers.fr/timings.html .
>> +            Most bitfields are unknown.
>> +            </doc>
>> +        <bitfield high="7" low="0" name="tRC">
>> +            <doc> Row Cycle time. </doc>
>> +        </bitfield>
>> +        <bitfield high="15" low="8" name="tRFC">
>> +            <doc> Refresh to activate delay. </doc>
>> +        </bitfield>
>> +        <bitfield high="23" low="17" name="tRAS">
>> +            <doc> Activate to precharge delay. </doc>
>> +        </bitfield>
>> +        <bitfield high="31" low="24" name="tRCD">
>> +            <doc> RAS# to CAS# Delay. </doc>
>>           </bitfield>
>>       </reg32>
>>         <reg32 offset="0x294" name="MEM_TIMINGS_1" variants="NVC0-">
>> +        <bitfield high="3" low="0" name="tCL">
>> +            <doc> Row Cycle time. </doc>
>> +        </bitfield>
>> +        <bitfield high="13" low="7" name="tCWL">
>> +            <doc> CAS# Write Latency. </doc>
>> +        </bitfield>
>>       </reg32>
>>         <reg32 offset="0x298" name="MEM_TIMINGS_2" variants="NVC0-">
>> +        <bitfield high="15" low="8" name="tWTR">
>> +            <doc> Write To Read delay. </doc>
>> +        </bitfield>
>> +        <bitfield high="23" low="15" name="tWR">
>> +            <doc> Write Recovery time. </doc>
>> +        </bitfield>
>>       </reg32>
>>         <reg32 offset="0x29c" name="MEM_TIMINGS_3" variants="NVC0-">
>
> Thanks for the patch but where did you get this knowledge? By 
> comparing with nv50 and the vbios table?

It's based on the code in nvbios.c:

                         reg_100220 = (tRCD << 24 | (tRAS&0x7f) << 17 | 
tRFC << 8 | tRC);
                         reg_100224 = 0x4c << 24 | (tUNK_11&0x0f) << 20 
| (tCWL << 7) | (tCL & 0x0f);
                         reg_100228 = 0x44000011 | tWR << 16 | tWTR << 8;
                         reg_10022c = tUNK_20 << 9 | tUNK_13;
                         reg_100230 = 0x42e00069 | tUNK_12 << 15;

                         printf("Registers: 290: 0x%08x 0x%08x 0x%08x 
0x%08x\n",
                         reg_100220, reg_100224,
                         reg_100228, reg_10022c);
                         printf("           2a0: 0x%08x 0x%08x 0x%08x 
0x%08x\n",
                         reg_100230, reg_100234,
                         reg_100238, reg_10023c);