[Nouveau] Questions about some PFB registers on NVAC cards

[Pierre Moreau]

Hi Robert,

Thanks a lot for your response!

----- Mail original -----
> On Wed, Oct 22, 2014 at 12:55:23AM +0200, pierre.morrow at free.fr
> wrote:
> [...]
> > After some investigation, I found that enabling bit 1 of register
> > 100c14 fixes
> > the issue on that card. Other NVAC cards are working great without
> > that trick,
> > and it seems they have that bit enabled by default. What is the
> > role of that
> > bit, and when should it be turned on?
> 
> Register 100c14 controls a feature of the integrated GPU's memory
> interface
> called the "poller".  The pollers exist on MCP77/78 and MCP79/7A to
> ensure
> that certain types of writes have flushed all the way to system
> memory.  (I
> think this is needed to ensure proper ordering of memory
> transactions.)
> 
> There are actually three important bits in that register, which
> control three
> pollers:
> 
> NV_PFB_NISO_POLLER_CFG
>                                                0x00100c14
> NV_PFB_NISO_POLLER_CFG_DNISO_ENABLE
>                                          0:0
> NV_PFB_NISO_POLLER_CFG_DNISO_ENABLE_DISABLED
>                          0x00000000
> NV_PFB_NISO_POLLER_CFG_DNISO_ENABLE_ENABLED
>                           0x00000001
> NV_PFB_NISO_POLLER_CFG_HOSTNB_ENABLE
>                                         1:1
> NV_PFB_NISO_POLLER_CFG_HOSTNB_ENABLE_DISABLED
>                         0x00000000
> NV_PFB_NISO_POLLER_CFG_HOSTNB_ENABLE_ENABLED
>                          0x00000001
> NV_PFB_NISO_POLLER_CFG_FLUSH_ENABLE
>                                        16:16
> NV_PFB_NISO_POLLER_CFG_FLUSH_ENABLE_DISABLED
>                          0x00000000
> NV_PFB_NISO_POLLER_CFG_FLUSH_ENABLE_ENABLED
>                           0x00000001
> 
> > Before enabling 100c14's bit 1, the Nvidia driver writes some value
> > into 100c1c.
> > Leaving the default value, or writing some random value seemed to
> > have no
> > effect. What is this register used for?
> 
> 100c1c is one of three registers which control the (upper bits of the
> 32-byte
> aligned) memory locations that the pollers use:
> 
> #define NV_PFB_NISO_POLLER_DNISO_BASE_ADR
>                     0x00100C18
> #define NV_PFB_NISO_POLLER_HOSTNB_BASE_ADR
>                    0x00100C1C
> #define NV_PFB_NISO_FLUSH_CARVEOUT_ADR
>                        0x00100C24
> 
> Each of these should point to at least 32 bytes of otherwise-unused
> FB
> memory, if the poller is enabled.
> 
> The proprietary driver enables all three pollers for GPUs that have
> them, when
> memory is not local (i.e., when using a sysmem carveout rather than
> dedicated
> video memory).
> 
> I'm not sure why this seems to only be necessary on some systems and
> not
> others.

I didn't meant that it wasn't necessary on other systems, just that it was enabled by default on those systems so they would work even if Nouveau didn't set the pollers.

> 
> - Robert
> 

Regards,

Pierre