[Nouveau] [PATCH RFC 19/20] sw/nv50: add some private functions to factorize code

[Samuel Pitoiset]

These functions will be also used by the interface for controlling
performance counters.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
---
 drm/nouveau/nvkm/engine/sw/nv50.c | 56 ++++++++++++++++++++++++++-------------
 1 file changed, 38 insertions(+), 18 deletions(-)

diff --git a/drm/nouveau/nvkm/engine/sw/nv50.c b/drm/nouveau/nvkm/engine/sw/nv50.c
index 401fcd7..b7c0227 100644
--- a/drm/nouveau/nvkm/engine/sw/nv50.c
+++ b/drm/nouveau/nvkm/engine/sw/nv50.c
@@ -36,27 +36,58 @@
  ******************************************************************************/
 
 static int
-nv50_sw_mthd_dma_vblsem(struct nvkm_object *object, u32 mthd,
-			void *args, u32 size)
+nv50_priv_ctxdma_get(struct nv50_sw_chan *chan, u32 name, u32 *ctxdma)
 {
-	struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
 	struct nvkm_fifo_chan *fifo = (void *)nv_object(chan)->parent;
 	struct nvkm_handle *handle;
 	int ret = -EINVAL;
 
-	handle = nvkm_namedb_get(nv_namedb(fifo), *(u32 *)args);
+	handle = nvkm_namedb_get(nv_namedb(fifo), name);
 	if (!handle)
 		return -ENOENT;
 
 	if (nv_iclass(handle->object, NV_GPUOBJ_CLASS)) {
 		struct nvkm_gpuobj *gpuobj = nv_gpuobj(handle->object);
-		chan->vblank.ctxdma = gpuobj->node->offset >> 4;
+		*ctxdma = gpuobj->node->offset >> 4;
 		ret = 0;
 	}
 	nvkm_namedb_put(handle);
 	return ret;
 }
 
+static void
+nv50_priv_ctxdma_flush(struct nv50_sw_chan *chan, u32 channel, u32 ctxdma)
+{
+	struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
+	struct nvkm_bar *bar = nvkm_bar(priv);
+
+	nv_wr32(priv, 0x001704, channel);
+	nv_wr32(priv, 0x001710, 0x80000000 | ctxdma);
+	bar->flush(bar);
+}
+
+static void
+nv50_priv_ctxdma_wr32(struct nv50_sw_chan *chan, u64 offset, u32 value)
+{
+	struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
+
+	if (nv_device(priv)->chipset == 0x50) {
+		nv_wr32(priv, 0x001570, offset);
+		nv_wr32(priv, 0x001574, value);
+	} else {
+		nv_wr32(priv, 0x060010, offset);
+		nv_wr32(priv, 0x060014, value);
+	}
+}
+
+static int
+nv50_sw_mthd_dma_vblsem(struct nvkm_object *object, u32 mthd,
+			void *args, u32 size)
+{
+	struct nv50_sw_chan *chan = (void *)nv_engctx(object->parent);
+	return nv50_priv_ctxdma_get(chan, *(u32 *)args, &chan->vblank.ctxdma);
+}
+
 static int
 nv50_sw_mthd_vblsem_offset(struct nvkm_object *object, u32 mthd,
 			   void *args, u32 size)
@@ -122,20 +153,9 @@ nv50_sw_vblsem_release(struct nvkm_notify *notify)
 {
 	struct nv50_sw_chan *chan =
 		container_of(notify, typeof(*chan), vblank.notify[notify->index]);
-	struct nv50_sw_priv *priv = (void *)nv_object(chan)->engine;
-	struct nvkm_bar *bar = nvkm_bar(priv);
-
-	nv_wr32(priv, 0x001704, chan->vblank.channel);
-	nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
-	bar->flush(bar);
 
-	if (nv_device(priv)->chipset == 0x50) {
-		nv_wr32(priv, 0x001570, chan->vblank.offset);
-		nv_wr32(priv, 0x001574, chan->vblank.value);
-	} else {
-		nv_wr32(priv, 0x060010, chan->vblank.offset);
-		nv_wr32(priv, 0x060014, chan->vblank.value);
-	}
+	nv50_priv_ctxdma_flush(chan, chan->vblank.channel, chan->vblank.ctxdma);
+	nv50_priv_ctxdma_wr32(chan, chan->vblank.offset, chan->vblank.value);
 
 	return NVKM_NOTIFY_DROP;
 }
-- 
2.4.2