[Nouveau] [PATCH v2 4/9] pci: implement pcie speed change for tesla

[Ben Skeggs]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA256

On 10/13/2015 07:44 PM, Karol Herbst wrote:
> v2: rename functions and simplify init
> 
> Signed-off-by: Karol Herbst <nouveau at karolherbst.de> --- 
> drm/nouveau/nvkm/subdev/pci/g84.c   | 105
> ++++++++++++++++++++++++++++++++++++ 
> drm/nouveau/nvkm/subdev/pci/g94.c   |  10 ++++ 
> drm/nouveau/nvkm/subdev/pci/gf100.c |   5 ++ 
> drm/nouveau/nvkm/subdev/pci/gf106.c |   5 ++ 
> drm/nouveau/nvkm/subdev/pci/gk104.c |   2 + 
> drm/nouveau/nvkm/subdev/pci/priv.h  |   9 ++++ 6 files changed, 136
> insertions(+)
> 
> diff --git a/drm/nouveau/nvkm/subdev/pci/g84.c
> b/drm/nouveau/nvkm/subdev/pci/g84.c index 3faa6bf..7a4e766 100644 
> --- a/drm/nouveau/nvkm/subdev/pci/g84.c +++
> b/drm/nouveau/nvkm/subdev/pci/g84.c @@ -25,6 +25,94 @@
> 
> #include <core/pci.h>
> 
> +int +g84_pcie_version_supported(struct nvkm_pci *pci) +{ +	u32
> chipset = pci->subdev.device->chipset, reg_v; + +	/* these cards
> report wrong information about what they support */ +	if (chipset
> == 0x84 || chipset == 0x86) +		return 1;
Give these chipsets their own implementation that just returns 1 for
this hook.

> + +	reg_v = nvkm_pci_rd32(pci, 0x460) & 0x200; +	if (reg_v ==
> 0x200) +		return 2; +	return 1; +} + +int +g84_pcie_version(struct
> nvkm_pci *pci) +{ +	struct nvkm_device *device =
> pci->subdev.device; +	return (nvkm_rd32(device, 0x00154c) & 0x1) +
> 1; +} + +void +g84_pcie_set_version(struct nvkm_pci *pci, u8 ver) 
> +{ +	struct nvkm_device *device = pci->subdev.device; +
> nvkm_mask(device, 0x00154c, 0x1, (ver >= 2 ? 0x1 : 0x0)); +} + 
> +static void +g84_pcie_set_cap_speed(struct nvkm_pci *pci, bool
> full_speed) +{ +	struct nvkm_device *device = pci->subdev.device; +
> nvkm_mask(device, 0x00154c, 0x80, full_speed ? 0x80 : 0x0); +} + 
> +enum nvkm_pcie_speed +g84_pcie_cur_speed(struct nvkm_pci *pci) +{ 
> +	u32 reg_v = nvkm_pci_rd32(pci, 0x88) & 0x30000; +	switch (reg_v)
> { +		case 0x30000: +			return NVKM_PCIE_SPEED_8_0; +		case
> 0x20000: +			return NVKM_PCIE_SPEED_5_0; +		case 0x10000: +
> default: +			return NVKM_PCIE_SPEED_2_5; +	} +} + +enum
> nvkm_pcie_speed +g84_pcie_max_speed(struct nvkm_pci *pci) +{ +	u32
> reg_v = nvkm_pci_rd32(pci, 0x460) & 0x3300; +	if (reg_v == 0x2200) 
> +		return NVKM_PCIE_SPEED_5_0; +	return NVKM_PCIE_SPEED_2_5; +} + 
> +void +g84_pcie_set_link_speed(struct nvkm_pci *pci, enum
> nvkm_pcie_speed speed) +{ +	u32 mask_value; + +	if (speed ==
> NVKM_PCIE_SPEED_5_0) +		mask_value = 0x20; +	else +		mask_value =
> 0x10; + +	nvkm_pci_mask(pci, 0x460, 0x30, mask_value); +
> nvkm_pci_mask(pci, 0x460, 0x1, 0x1); +} + +int 
> +g84_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed
> req_speed, +	u8 req_width) +{ +	if (req_speed ==
> NVKM_PCIE_SPEED_5_0) +		g84_pcie_set_cap_speed(pci, true); +	else +
> g84_pcie_set_cap_speed(pci, false); + +
> g84_pcie_set_link_speed(pci, req_speed); + +	return 0; +} + void 
> g84_pci_init(struct nvkm_pci *pci) { @@ -48,6 +136,13 @@
> g84_pci_init(struct nvkm_pci *pci) nvkm_pci_mask(pci, 0x041c,
> 0x00000060, 0x00000000); }
> 
> +int +g84_pcie_init(struct nvkm_pci *pci) +{ +
> g84_pcie_set_cap_speed(pci, g84_pcie_cur_speed(pci) ==
> NVKM_PCIE_SPEED_5_0); +	return 0; +} + static const struct
> nvkm_pci_func g84_pci_func = { .init = g84_pci_init, @@ -55,6
> +150,16 @@ g84_pci_func = { .wr08 = nv40_pci_wr08, .wr32 =
> nv40_pci_wr32, .msi_rearm = nv46_pci_msi_rearm, + +	.pcie.init =
> g84_pcie_init, +	.pcie.set_link = g84_pcie_set_link, + +
> .pcie.max_speed = g84_pcie_max_speed, +	.pcie.cur_speed =
> g84_pcie_cur_speed, + +	.pcie.set_version = g84_pcie_set_version, +
> .pcie.version = g84_pcie_version, +	.pcie.version_supported =
> g84_pcie_version_supported, };
> 
> int diff --git a/drm/nouveau/nvkm/subdev/pci/g94.c
> b/drm/nouveau/nvkm/subdev/pci/g94.c index cd311ee..f2f96c1 100644 
> --- a/drm/nouveau/nvkm/subdev/pci/g94.c +++
> b/drm/nouveau/nvkm/subdev/pci/g94.c @@ -30,6 +30,16 @@ g94_pci_func
> = { .wr08 = nv40_pci_wr08, .wr32 = nv40_pci_wr32, .msi_rearm =
> nv40_pci_msi_rearm, + +	.pcie.init = g84_pcie_init, +
> .pcie.set_link = g84_pcie_set_link, + +	.pcie.max_speed =
> g84_pcie_max_speed, +	.pcie.cur_speed = g84_pcie_cur_speed, + +
> .pcie.set_version = g84_pcie_set_version, +	.pcie.version =
> g84_pcie_version, +	.pcie.version_supported =
> g84_pcie_version_supported, };
> 
> int diff --git a/drm/nouveau/nvkm/subdev/pci/gf100.c
> b/drm/nouveau/nvkm/subdev/pci/gf100.c index 25e1ae7..1ee43ad
> 100644 --- a/drm/nouveau/nvkm/subdev/pci/gf100.c +++
> b/drm/nouveau/nvkm/subdev/pci/gf100.c @@ -36,6 +36,11 @@
> gf100_pci_func = { .wr08 = nv40_pci_wr08, .wr32 = nv40_pci_wr32, 
> .msi_rearm = gf100_pci_msi_rearm, + +	.pcie.max_speed =
> g84_pcie_max_speed, +	.pcie.cur_speed = g84_pcie_cur_speed, + +
> .pcie.version_supported = g84_pcie_version_supported, };
> 
> int diff --git a/drm/nouveau/nvkm/subdev/pci/gf106.c
> b/drm/nouveau/nvkm/subdev/pci/gf106.c index 82d8c27..d72f850
> 100644 --- a/drm/nouveau/nvkm/subdev/pci/gf106.c +++
> b/drm/nouveau/nvkm/subdev/pci/gf106.c @@ -29,6 +29,11 @@
> gf106_pci_func = { .wr08 = nv40_pci_wr08, .wr32 = nv40_pci_wr32, 
> .msi_rearm = nv40_pci_msi_rearm, + +	.pcie.max_speed =
> g84_pcie_max_speed, +	.pcie.cur_speed = g84_pcie_cur_speed, + +
> .pcie.version_supported = g84_pcie_version_supported, };
> 
> int diff --git a/drm/nouveau/nvkm/subdev/pci/gk104.c
> b/drm/nouveau/nvkm/subdev/pci/gk104.c index 6119f89..af79d9b
> 100644 --- a/drm/nouveau/nvkm/subdev/pci/gk104.c +++
> b/drm/nouveau/nvkm/subdev/pci/gk104.c @@ -29,6 +29,8 @@
> gk104_pci_func = { .wr08 = nv40_pci_wr08, .wr32 = nv40_pci_wr32, 
> .msi_rearm = nv40_pci_msi_rearm, + +	.pcie.cur_speed =
> g84_pcie_cur_speed, };
> 
> int diff --git a/drm/nouveau/nvkm/subdev/pci/priv.h
> b/drm/nouveau/nvkm/subdev/pci/priv.h index 5370f0d..a504812 100644 
> --- a/drm/nouveau/nvkm/subdev/pci/priv.h +++
> b/drm/nouveau/nvkm/subdev/pci/priv.h @@ -36,5 +36,14 @@ void
> nv46_pci_msi_rearm(struct nvkm_pci *); void g84_pci_init(struct
> nvkm_pci *pci);
> 
> /* pcie functions */ +void g84_pcie_set_version(struct nvkm_pci *,
> u8); +int g84_pcie_version(struct nvkm_pci *); +int
> g84_pcie_version_supported(struct nvkm_pci *); +void
> g84_pcie_set_link_speed(struct nvkm_pci *, enum nvkm_pcie_speed); 
> +enum nvkm_pcie_speed g84_pcie_cur_speed(struct nvkm_pci *); +enum
> nvkm_pcie_speed g84_pcie_max_speed(struct nvkm_pci *); +int
> g84_pcie_init(struct nvkm_pci *); +int g84_pcie_set_link(struct
> nvkm_pci *, enum nvkm_pcie_speed, u8); + int nvkm_pcie_init(struct
> nvkm_pci *pci); #endif
> 
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2

iQIcBAEBCAAGBQJWHYwoAAoJEHYLnGJQkpH7V7wP/ArjtKXGn6CDPgDGp+a40BWc
mB4T3dLjgZhjGYVjbPG0eddynTiR4PyJP+RPyD0O4eS+PdknUMo+QJXPOYWVoKlg
a090vfzkAp35OSSRa6NjKOAf5LgK4+Zi6BgFXE3TpUJ6w2vxOkUIUDLOaC3HPc61
Kk1TqPEcKk8JCl7fHGmzt8gPhw/bJaDzDmFghudzpVzJit0jXzAkevqHN80y4Auz
ADYE0ayVPPG0hDEGIXhY09A2OZPbfAqJyP2A0mt97ELWsUc1w1ipjz3Psq0u6QvB
fCHX4FPp6a1Lbns0M3a+RWOOeVv7zciOcmrDGSvmiX2IbvnoFDzK+fK6/MadLFk5
2Sh5hdH6e6T5BLKetCU/A9JWF/RdytQF8GHZEYxr0aM6NINKyB+jU1ccAkRqJLmm
+sbd9ONkfbWVuweTeiQW7I4fBHI9+LVbdcMusnTREKsFK5mri4SRAovKTq20WKKp
EGGHzeJlm7YQVJg5JZGfK2FcCxE9yTkthK3mKYHI/c4HufyL+JMHfAJo1hKO3xL4
vAnmq2XoUltPJyNqzsTJMt8zooraXYEMaVfpzijE3A1B5wm+e5/7DpNNhcDZT86K
AvLj+bxQ3+B0Z74jfy2jUNerwiImKH/aFsa681kVlX7Y57fXcc1AaUXqLEwshQGp
FUxQj+UWJ/GIcImWaNVW
=6Pdy
-----END PGP SIGNATURE-----