[Nouveau] [PATCH v4 26/33] pmu: support for GM20B signed firmware
Alexandre Courbot
acourbot at nvidia.com
Mon Nov 21 08:29:23 UTC 2016
From: Deepak Goyal <dgoyal at nvidia.com>
Add support for the message format used by the GM20B signed PMU
firmware.
Signed-off-by: Deepak Goyal <dgoyal at nvidia.com>
[acourbot at nvidia.com: reorganize code]
Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>
---
drm/nouveau/nvkm/subdev/pmu/Kbuild | 2 +-
drm/nouveau/nvkm/subdev/pmu/base.c | 3 +-
drm/nouveau/nvkm/subdev/pmu/nv_0137c63d.c | 255 +++++++++++++++++++++++-
drm/nouveau/nvkm/subdev/pmu/nv_pmu.h | 3 +-
drm/nouveau/nvkm/subdev/pmu/priv.h | 2 +-
5 files changed, 265 insertions(+), 0 deletions(-)
create mode 100644 drm/nouveau/nvkm/subdev/pmu/nv_0137c63d.c
diff --git a/drm/nouveau/nvkm/subdev/pmu/Kbuild b/drm/nouveau/nvkm/subdev/pmu/Kbuild
index 141f3ee6ffe4..b20328cf897e 100644
--- a/drm/nouveau/nvkm/subdev/pmu/Kbuild
+++ b/drm/nouveau/nvkm/subdev/pmu/Kbuild
@@ -11,3 +11,5 @@ nvkm-y += nvkm/subdev/pmu/gm107.o
nvkm-y += nvkm/subdev/pmu/gm200.o
nvkm-y += nvkm/subdev/pmu/gp100.o
nvkm-y += nvkm/subdev/pmu/gp102.o
+
+nvkm-y += nvkm/subdev/pmu/nv_0137c63d.o
diff --git a/drm/nouveau/nvkm/subdev/pmu/base.c b/drm/nouveau/nvkm/subdev/pmu/base.c
index 20bd5585df15..0ca9cafb18c0 100644
--- a/drm/nouveau/nvkm/subdev/pmu/base.c
+++ b/drm/nouveau/nvkm/subdev/pmu/base.c
@@ -156,6 +156,9 @@ nvkm_pmu_set_version(struct nvkm_pmu *pmu, u32 version)
return -ENODEV;
switch (version) {
+ case 0x0137c63d:
+ pmu->nv_func = &nv_0137c63d_func;
+ break;
default:
nvkm_error(subdev, "unhandled firmware version 0x%08x\n",
version);
diff --git a/drm/nouveau/nvkm/subdev/pmu/nv_0137c63d.c b/drm/nouveau/nvkm/subdev/pmu/nv_0137c63d.c
new file mode 100644
index 000000000000..522f8624e1de
--- /dev/null
+++ b/drm/nouveau/nvkm/subdev/pmu/nv_0137c63d.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "gm200.h"
+#include "nv_pmu.h"
+
+/**
+ * struct pmu_cmdline_args - PMU ucode commandline DMEM arguments
+ * @freq_hz: freq at which PMU falcon runs (Hz)
+ * @trace_buf: trace buf memory descriptor. Trace buffer can be used
+ * to dump traces from PMU ucode.
+ * @secure_mode: total size of the code part in the ucode
+ * @raise_priv_sec: raise priv level required for desired regs
+ * @gc6_ctx: dma info for GC6 context
+ * @init_data_dma_info: dma info for INIT data surface.
+ *
+ * Structure used for Global command-line arguments for the PMU
+ */
+struct pmu_cmdline_args {
+ u32 reserved;
+ u32 freq_hz;
+ u32 trace_size;
+ u32 trace_dma_base;
+ u16 trace_dma_base1;
+ u8 trace_dma_offset;
+ u32 trace_dma_idx;
+ bool secure_mode;
+ bool raise_priv_sec;
+ struct {
+ u32 dma_base;
+ u16 dma_base1;
+ u8 dma_offset;
+ u16 fb_size;
+ u8 dma_idx;
+ } gc6_ctx;
+ u8 pad;
+};
+
+static void
+pmu_gen_cmdline(struct nvkm_pmu *pmu, void *buf)
+{
+ struct pmu_cmdline_args *args = buf;
+
+ args->secure_mode = 1;
+}
+
+enum {
+ PMU_INIT_MSG_TYPE_PMU_INIT = 0x0,
+};
+
+struct pmu_init_msg {
+ struct pmu_msg_base base;
+
+ u8 pad;
+ u16 os_debug_entry_point;
+
+ struct {
+ u16 size;
+ u16 offset;
+ u8 index;
+ u8 pad;
+ } queue_info[GM200_PMU_QUEUE_COUNT];
+
+ u16 sw_managed_area_offset;
+ u16 sw_managed_area_size;
+ struct {
+ bool is_valid;
+ u8 version;
+ u32 status;
+ u8 hulk_data[4];
+ u32 vpr_data[2];
+ } brsdata;
+};
+
+static int
+pmu_init_callback(struct nvkm_pmu *pmu, struct pmu_hdr *hdr)
+{
+ struct pmu_init_msg *init = (void *)hdr;
+ struct gm200_pmu *priv = gm200_pmu(pmu);
+ struct nvkm_subdev *subdev = &pmu->subdev;
+ int i;
+
+ if (init->base.msg_type != PMU_INIT_MSG_TYPE_PMU_INIT) {
+ nvkm_error(subdev, "expected PMU init msg\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < GM200_PMU_QUEUE_COUNT; i++) {
+ struct gm200_pmu_queue *queue = &priv->queue[i];
+
+ queue->id = i;
+ queue->index = init->queue_info[i].index;
+ queue->offset = init->queue_info[i].offset;
+ queue->size = init->queue_info[i].size;
+ mutex_init(&queue->mutex);
+ }
+
+ return 0;
+}
+
+const struct nv_pmu_init_func
+nv_0137c63d_init_func = {
+ .cmdline_size = sizeof(struct pmu_cmdline_args),
+ .gen_cmdline = pmu_gen_cmdline,
+ .init_callback = pmu_init_callback,
+};
+
+/* ACR commands */
+enum {
+ PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0,
+ PMU_ACR_CMD_ID_BOOTSTRAP_FALCON,
+};
+
+struct acr_init_wpr_msg {
+ struct pmu_msg_base base;
+
+ u32 error_code;
+};
+
+static void
+acr_init_wpr_callback(struct nvkm_pmu *pmu, struct pmu_hdr *hdr)
+{
+ struct acr_init_wpr_msg *msg = (void *)hdr;
+ struct nvkm_subdev *subdev = &pmu->subdev;
+ struct gm200_pmu *priv = gm200_pmu(pmu);
+
+ if (msg->error_code) {
+ nvkm_error(subdev, "ACR WPR init failure: %d\n",
+ msg->error_code);
+ return;
+ }
+
+ nvkm_debug(subdev, "ACR WPR init complete\n");
+ complete_all(&priv->init_done);
+}
+
+static int
+acr_init_wpr(struct nvkm_pmu *pmu)
+{
+ /*
+ * regionid - specifying region ID in WPR.
+ * wpr_offset - wpr offset in WPR region.
+ */
+ struct {
+ struct pmu_hdr hdr;
+ u8 cmd_type;
+ u32 region_id;
+ u32 wpr_offset;
+ } cmd;
+ memset(&cmd, 0, sizeof(cmd));
+
+ cmd.hdr.unit_id = PMU_UNIT_ACR;
+ cmd.hdr.size = sizeof(cmd);
+ cmd.cmd_type = PMU_ACR_CMD_ID_INIT_WPR_REGION;
+ cmd.region_id = 0x01;
+ cmd.wpr_offset = 0x00;
+
+ nv_pmu_cmd_post(pmu, &cmd.hdr, NULL, PMU_COMMAND_QUEUE_HPQ,
+ acr_init_wpr_callback, NULL);
+
+ return 0;
+}
+
+struct acr_bootstrap_falcon_msg {
+ struct pmu_msg_base base;
+
+ u32 falcon_id;
+};
+
+static void
+acr_boot_falcon_callback(struct nvkm_pmu *pmu, struct pmu_hdr *hdr)
+{
+ struct acr_bootstrap_falcon_msg *msg = (void *)hdr;
+ struct nvkm_subdev *subdev = &pmu->subdev;
+ u32 falcon_id = msg->falcon_id;
+
+ if (falcon_id >= NVKM_FALCON_END) {
+ nvkm_error(subdev, "in bootstrap falcon callback:\n");
+ nvkm_error(subdev, "invalid falcon ID 0x%x\n", falcon_id);
+ return;
+ }
+ nvkm_debug(subdev, "%s booted\n", nvkm_falcon_name[falcon_id]);
+}
+
+enum {
+ ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES = 0,
+ ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO = 1,
+};
+
+static int
+acr_boot_falcon(struct nvkm_pmu *pmu, enum nvkm_falconidx falcon)
+{
+ struct gm200_pmu *priv = gm200_pmu(pmu);
+ DECLARE_COMPLETION_ONSTACK(completed);
+ /*
+ * flags - Flag specifying RESET or no RESET.
+ * falcon id - Falcon id specifying falcon to bootstrap.
+ */
+ struct {
+ struct pmu_hdr hdr;
+ u8 cmd_type;
+ u32 flags;
+ u32 falcon_id;
+ } cmd;
+
+ if (!wait_for_completion_timeout(&priv->init_done,
+ msecs_to_jiffies(1000)))
+ return -ETIMEDOUT;
+
+ memset(&cmd, 0, sizeof(cmd));
+
+ cmd.hdr.unit_id = PMU_UNIT_ACR;
+ cmd.hdr.size = sizeof(cmd);
+ cmd.cmd_type = PMU_ACR_CMD_ID_BOOTSTRAP_FALCON;
+ cmd.flags = ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
+ cmd.falcon_id = falcon;
+ nv_pmu_cmd_post(pmu, &cmd.hdr, NULL, PMU_COMMAND_QUEUE_HPQ,
+ acr_boot_falcon_callback, &completed);
+
+ if (!wait_for_completion_timeout(&completed, msecs_to_jiffies(1000)))
+ return -ETIMEDOUT;
+
+ return 0;
+}
+
+const struct nv_pmu_acr_func
+nv_0137c63d_acr_func = {
+ .init_wpr_region = acr_init_wpr,
+ .boot_falcon = acr_boot_falcon,
+};
+
+const struct nv_pmu_func
+nv_0137c63d_func = {
+ .init = &nv_0137c63d_init_func,
+ .acr = &nv_0137c63d_acr_func,
+};
diff --git a/drm/nouveau/nvkm/subdev/pmu/nv_pmu.h b/drm/nouveau/nvkm/subdev/pmu/nv_pmu.h
index 4267952231f7..fb8168f3e564 100644
--- a/drm/nouveau/nvkm/subdev/pmu/nv_pmu.h
+++ b/drm/nouveau/nvkm/subdev/pmu/nv_pmu.h
@@ -44,6 +44,9 @@ enum nv_pmu_queue {
PMU_MESSAGE_QUEUE = 4,
};
+extern const struct nv_pmu_init_func nv_0137c63d_init_func;
+extern const struct nv_pmu_acr_func nv_0137c63d_acr_func;
+
int nv_pmu_cmd_post(struct nvkm_pmu *, struct pmu_hdr *, struct pmu_hdr *,
enum nv_pmu_queue, nv_pmu_callback, struct completion *);
diff --git a/drm/nouveau/nvkm/subdev/pmu/priv.h b/drm/nouveau/nvkm/subdev/pmu/priv.h
index b93b300a101a..4eb29c2ec785 100644
--- a/drm/nouveau/nvkm/subdev/pmu/priv.h
+++ b/drm/nouveau/nvkm/subdev/pmu/priv.h
@@ -55,5 +55,7 @@ struct nv_pmu_func {
const struct nv_pmu_acr_func *acr;
};
+extern const struct nv_pmu_func nv_0137c63d_func;
+
void gk110_pmu_pgob(struct nvkm_pmu *, bool);
#endif
--
git-series 0.8.10
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