[Nouveau] [PATCH 6/9] clk: Split out update code to nv40
Karol Herbst
karolherbst at gmail.com
Sun Mar 5 16:35:04 UTC 2017
This code will change for gf100 and newer for partial reclocks.
Signed-off-by: Karol Herbst <karolherbst at gmail.com>
Reviewed-by: Martin Peres <martin.peres at free.fr>
---
drm/nouveau/nvkm/subdev/clk/base.c | 15 ++++++---------
drm/nouveau/nvkm/subdev/clk/g84.c | 1 +
drm/nouveau/nvkm/subdev/clk/gf100.c | 1 +
drm/nouveau/nvkm/subdev/clk/gk104.c | 1 +
drm/nouveau/nvkm/subdev/clk/gk20a.c | 1 +
drm/nouveau/nvkm/subdev/clk/gm20b.c | 1 +
drm/nouveau/nvkm/subdev/clk/gt215.c | 1 +
drm/nouveau/nvkm/subdev/clk/mcp77.c | 1 +
drm/nouveau/nvkm/subdev/clk/nv40.c | 18 ++++++++++++++++++
drm/nouveau/nvkm/subdev/clk/nv50.c | 1 +
drm/nouveau/nvkm/subdev/clk/priv.h | 5 +++++
11 files changed, 37 insertions(+), 9 deletions(-)
diff --git a/drm/nouveau/nvkm/subdev/clk/base.c b/drm/nouveau/nvkm/subdev/clk/base.c
index 1d71bf09..b81b0258 100644
--- a/drm/nouveau/nvkm/subdev/clk/base.c
+++ b/drm/nouveau/nvkm/subdev/clk/base.c
@@ -271,7 +271,7 @@ nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate)
/******************************************************************************
* P-States
*****************************************************************************/
-static int
+int
nvkm_pstate_prog(struct nvkm_clk *clk, int pstateid)
{
struct nvkm_subdev *subdev = &clk->subdev;
@@ -319,6 +319,10 @@ nvkm_clk_update_work(struct work_struct *work)
if (!atomic_xchg(&clk->waiting, 0))
return;
+
+ if (!clk->func->update)
+ return;
+
clk->pwrsrc = power_supply_is_system_supplied();
if (clk->pstate)
@@ -336,14 +340,7 @@ nvkm_clk_update_work(struct work_struct *work)
pstate = NVKM_CLK_PSTATE_DEFAULT;
}
- nvkm_trace(subdev, "-> %d\n", pstate);
- if (!clk->pstate || pstate != clk->pstate->pstate) {
- int ret = nvkm_pstate_prog(clk, pstate);
- if (ret) {
- nvkm_error(subdev, "error setting pstate %d: %d\n",
- pstate, ret);
- }
- }
+ clk->func->update(clk, pstate);
wake_up_all(&clk->wait);
nvkm_notify_get(&clk->pwrsrc_ntfy);
diff --git a/drm/nouveau/nvkm/subdev/clk/g84.c b/drm/nouveau/nvkm/subdev/clk/g84.c
index f97e3ec1..7b9b30d2 100644
--- a/drm/nouveau/nvkm/subdev/clk/g84.c
+++ b/drm/nouveau/nvkm/subdev/clk/g84.c
@@ -29,6 +29,7 @@ g84_clk = {
.calc = nv50_clk_calc,
.prog = nv50_clk_prog,
.tidy = nv50_clk_tidy,
+ .update = nv40_clk_update,
.domains = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
diff --git a/drm/nouveau/nvkm/subdev/clk/gf100.c b/drm/nouveau/nvkm/subdev/clk/gf100.c
index 7f67f9f5..8a46bf80 100644
--- a/drm/nouveau/nvkm/subdev/clk/gf100.c
+++ b/drm/nouveau/nvkm/subdev/clk/gf100.c
@@ -451,6 +451,7 @@ gf100_clk = {
.calc = gf100_clk_calc,
.prog = gf100_clk_prog,
.tidy = gf100_clk_tidy,
+ .update = nv40_clk_update,
.domains = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
diff --git a/drm/nouveau/nvkm/subdev/clk/gk104.c b/drm/nouveau/nvkm/subdev/clk/gk104.c
index 0b37e3da..cae58b6a 100644
--- a/drm/nouveau/nvkm/subdev/clk/gk104.c
+++ b/drm/nouveau/nvkm/subdev/clk/gk104.c
@@ -488,6 +488,7 @@ gk104_clk = {
.calc = gk104_clk_calc,
.prog = gk104_clk_prog,
.tidy = gk104_clk_tidy,
+ .update = nv40_clk_update,
.domains = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
diff --git a/drm/nouveau/nvkm/subdev/clk/gk20a.c b/drm/nouveau/nvkm/subdev/clk/gk20a.c
index 218893e3..ae40675b 100644
--- a/drm/nouveau/nvkm/subdev/clk/gk20a.c
+++ b/drm/nouveau/nvkm/subdev/clk/gk20a.c
@@ -600,6 +600,7 @@ gk20a_clk = {
.calc = gk20a_clk_calc,
.prog = gk20a_clk_prog,
.tidy = gk20a_clk_tidy,
+ .update = nv40_clk_update,
.pstates = gk20a_pstates,
.nr_pstates = ARRAY_SIZE(gk20a_pstates),
.domains = {
diff --git a/drm/nouveau/nvkm/subdev/clk/gm20b.c b/drm/nouveau/nvkm/subdev/clk/gm20b.c
index b284e949..74346c88 100644
--- a/drm/nouveau/nvkm/subdev/clk/gm20b.c
+++ b/drm/nouveau/nvkm/subdev/clk/gm20b.c
@@ -880,6 +880,7 @@ gm20b_clk_speedo0 = {
.calc = gk20a_clk_calc,
.prog = gk20a_clk_prog,
.tidy = gk20a_clk_tidy,
+ .update = nv40_clk_update,
.pstates = gm20b_pstates,
/* Speedo 0 only supports 12 voltages */
.nr_pstates = ARRAY_SIZE(gm20b_pstates) - 1,
diff --git a/drm/nouveau/nvkm/subdev/clk/gt215.c b/drm/nouveau/nvkm/subdev/clk/gt215.c
index 96e0941c..7315b310 100644
--- a/drm/nouveau/nvkm/subdev/clk/gt215.c
+++ b/drm/nouveau/nvkm/subdev/clk/gt215.c
@@ -520,6 +520,7 @@ gt215_clk = {
.calc = gt215_clk_calc,
.prog = gt215_clk_prog,
.tidy = gt215_clk_tidy,
+ .update = nv40_clk_update,
.domains = {
{ nv_clk_src_crystal , 0xff },
{ nv_clk_src_core , 0x00, 0, "core", 1000 },
diff --git a/drm/nouveau/nvkm/subdev/clk/mcp77.c b/drm/nouveau/nvkm/subdev/clk/mcp77.c
index 1c21b8b5..e80b68e9 100644
--- a/drm/nouveau/nvkm/subdev/clk/mcp77.c
+++ b/drm/nouveau/nvkm/subdev/clk/mcp77.c
@@ -400,6 +400,7 @@ mcp77_clk = {
.calc = mcp77_clk_calc,
.prog = mcp77_clk_prog,
.tidy = mcp77_clk_tidy,
+ .update = nv40_clk_update,
.domains = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
diff --git a/drm/nouveau/nvkm/subdev/clk/nv40.c b/drm/nouveau/nvkm/subdev/clk/nv40.c
index 2ab9b9b8..15768996 100644
--- a/drm/nouveau/nvkm/subdev/clk/nv40.c
+++ b/drm/nouveau/nvkm/subdev/clk/nv40.c
@@ -201,12 +201,30 @@ nv40_clk_tidy(struct nvkm_clk *obj)
{
}
+void
+nv40_clk_update(struct nvkm_clk *clk, int pstate)
+{
+ struct nvkm_subdev *subdev = &clk->subdev;
+ int ret;
+
+ if (clk->pstate && pstate == clk->pstate->pstate)
+ return;
+
+ nvkm_trace(subdev, "-> %d\n", pstate);
+ ret = nvkm_pstate_prog(clk, pstate);
+ if (ret) {
+ nvkm_error(subdev, "error setting pstate %d: %d\n",
+ pstate, ret);
+ }
+}
+
static const struct nvkm_clk_func
nv40_clk = {
.read = nv40_clk_read,
.calc = nv40_clk_calc,
.prog = nv40_clk_prog,
.tidy = nv40_clk_tidy,
+ .update = nv40_clk_update,
.domains = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
diff --git a/drm/nouveau/nvkm/subdev/clk/nv50.c b/drm/nouveau/nvkm/subdev/clk/nv50.c
index da1770e4..130cfee0 100644
--- a/drm/nouveau/nvkm/subdev/clk/nv50.c
+++ b/drm/nouveau/nvkm/subdev/clk/nv50.c
@@ -544,6 +544,7 @@ nv50_clk = {
.calc = nv50_clk_calc,
.prog = nv50_clk_prog,
.tidy = nv50_clk_tidy,
+ .update = nv40_clk_update,
.domains = {
{ nv_clk_src_crystal, 0xff },
{ nv_clk_src_href , 0xff },
diff --git a/drm/nouveau/nvkm/subdev/clk/priv.h b/drm/nouveau/nvkm/subdev/clk/priv.h
index 51eafc00..958f5e35 100644
--- a/drm/nouveau/nvkm/subdev/clk/priv.h
+++ b/drm/nouveau/nvkm/subdev/clk/priv.h
@@ -10,6 +10,7 @@ struct nvkm_clk_func {
int (*calc)(struct nvkm_clk *, struct nvkm_cstate *);
int (*prog)(struct nvkm_clk *);
void (*tidy)(struct nvkm_clk *);
+ void (*update)(struct nvkm_clk *, int pstate);
struct nvkm_pstate *pstates;
int nr_pstates;
struct nvkm_domain domains[];
@@ -20,7 +21,11 @@ int nvkm_clk_ctor(const struct nvkm_clk_func *, struct nvkm_device *, int,
int nvkm_clk_new_(const struct nvkm_clk_func *, struct nvkm_device *, int,
bool allow_reclock, struct nvkm_clk **);
+int nvkm_pstate_prog(struct nvkm_clk *, int pstateid);
+
int nv04_clk_pll_calc(struct nvkm_clk *, struct nvbios_pll *, int clk,
struct nvkm_pll_vals *);
int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *);
+
+void nv40_clk_update(struct nvkm_clk *, int pstate);
#endif
--
2.12.0
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