[PATCH v3 23/25] drm/xe: Compute dumb-buffer sizes with drm_mode_size_dumb()
Matthew Auld
matthew.auld at intel.com
Thu Feb 20 10:08:33 UTC 2025
On 18/02/2025 14:23, Thomas Zimmermann wrote:
> Call drm_mode_size_dumb() to compute dumb-buffer scanline pitch
> and buffer size. Align the pitch to a multiple of 8. Align the
> buffer size according to hardware requirements.
>
> Xe's internal calculation allowed for 64-bit wide buffer sizes, but
> the ioctl's internal checks always verified against 32-bit wide limits.
> Hance, it is safe to limit the driver code to 32-bit calculations as
> well.
>
> v3:
> - mention 32-bit calculation in commit description (Matthew)
>
> Signed-off-by: Thomas Zimmermann <tzimmermann at suse.de>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: "Thomas Hellström" <thomas.hellstrom at linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
Reviewed-by: Matthew Auld <matthew.auld at intel.com>
> ---
> drivers/gpu/drm/xe/xe_bo.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
> index 78d09c5ed26d..b34f446ad57d 100644
> --- a/drivers/gpu/drm/xe/xe_bo.c
> +++ b/drivers/gpu/drm/xe/xe_bo.c
> @@ -9,6 +9,7 @@
> #include <linux/nospec.h>
>
> #include <drm/drm_drv.h>
> +#include <drm/drm_dumb_buffers.h>
> #include <drm/drm_gem_ttm_helper.h>
> #include <drm/drm_managed.h>
> #include <drm/ttm/ttm_device.h>
> @@ -2672,14 +2673,13 @@ int xe_bo_dumb_create(struct drm_file *file_priv,
> struct xe_device *xe = to_xe_device(dev);
> struct xe_bo *bo;
> uint32_t handle;
> - int cpp = DIV_ROUND_UP(args->bpp, 8);
> int err;
> u32 page_size = max_t(u32, PAGE_SIZE,
> xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K ? SZ_64K : SZ_4K);
>
> - args->pitch = ALIGN(args->width * cpp, 64);
> - args->size = ALIGN(mul_u32_u32(args->pitch, args->height),
> - page_size);
> + err = drm_mode_size_dumb(dev, args, SZ_64, page_size);
> + if (err)
> + return err;
>
> bo = xe_bo_create_user(xe, NULL, NULL, args->size,
> DRM_XE_GEM_CPU_CACHING_WC,
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