[PATCH v2 20/62] drm/nouveau/gsp: ignore client engine object handles
Ben Skeggs
bskeggs at nvidia.com
Sun May 11 21:06:40 UTC 2025
The next commit moves to using the hInternal{Client,Device,Subdevice}
objects (nearly) everywhere, rather than allocating new ones for each
client.
In order to avoid object handle collisions, generate an object handle
from object class and channel id instead of using the client-provided
handle.
This also effectively means it's not possible to allocate more than a
single object of a given class on a channel, but there's no reason to
do so on recent hardware anyway.
Signed-off-by: Ben Skeggs <bskeggs at nvidia.com>
Reviewed-by: Dave Airlie <airlied at redhat.com>
Reviewed-by: Timur Tabi <ttabi at nvidia.com>
Tested-by: Timur Tabi <ttabi at nvidia.com>
---
drivers/gpu/drm/nouveau/include/nvif/cl0080.h | 3 ++-
drivers/gpu/drm/nouveau/nouveau_abi16.c | 10 ++++++----
drivers/gpu/drm/nouveau/nvkm/engine/device/user.c | 2 ++
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c | 2 +-
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/handles.h | 1 +
5 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/include/nvif/cl0080.h b/drivers/gpu/drm/nouveau/include/nvif/cl0080.h
index ea937fa7bc55..bad124c15a5b 100644
--- a/drivers/gpu/drm/nouveau/include/nvif/cl0080.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/cl0080.h
@@ -30,7 +30,8 @@ struct nv_device_info_v0 {
#define NV_DEVICE_INFO_V0_AMPERE 0x0d
#define NV_DEVICE_INFO_V0_ADA 0x0e
__u8 family;
- __u8 pad06[2];
+ __u8 gsp_rm;
+ __u8 pad07;
__u64 ram_size;
__u64 ram_user;
char chip[16];
diff --git a/drivers/gpu/drm/nouveau/nouveau_abi16.c b/drivers/gpu/drm/nouveau/nouveau_abi16.c
index 2a0617e5fe2a..da8efe134f16 100644
--- a/drivers/gpu/drm/nouveau/nouveau_abi16.c
+++ b/drivers/gpu/drm/nouveau/nouveau_abi16.c
@@ -456,10 +456,12 @@ nouveau_abi16_ioctl_channel_alloc(ABI16_IOCTL_ARGS)
goto done;
break;
case NV_DEVICE_INFO_V0_TURING:
- ret = nvif_object_ctor(&chan->chan->user, "abi16CeWar", 0, TURING_DMA_COPY_A,
- NULL, 0, &chan->ce);
- if (ret)
- goto done;
+ if (!device->info.gsp_rm) {
+ ret = nvif_object_ctor(&chan->chan->user, "abi16CeWar", 0,
+ TURING_DMA_COPY_A, NULL, 0, &chan->ce);
+ if (ret)
+ goto done;
+ }
break;
default:
break;
diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
index d7f75b3a43c8..3651d9bf5655 100644
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
@@ -153,6 +153,8 @@ nvkm_udevice_info(struct nvkm_udevice *udev, void *data, u32 size)
break;
}
+ args->v0.gsp_rm = nvkm_gsp_rm(device->gsp);
+
args->v0.chipset = device->chipset;
args->v0.revision = device->chiprev;
if (fb && fb->ram)
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
index 3b0e83b2f57f..a073a5d03b65 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/engine.c
@@ -40,7 +40,7 @@ nvkm_rm_engine_obj_new(struct nvkm_gsp_object *chan, int chid, const struct nvkm
struct nvkm_rm *rm = chan->client->gsp->rm;
const int inst = oclass->engine->subdev.inst;
const u32 class = oclass->base.oclass;
- const u32 handle = oclass->handle;
+ const u32 handle = NVKM_RM_ENGOBJ(class, chid);
struct nvkm_rm_engine_obj *obj;
int ret;
diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/handles.h b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/handles.h
index 50f2f2a86b5a..66604474e339 100644
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/handles.h
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/handles.h
@@ -14,4 +14,5 @@
#define NVKM_RM_VASPACE 0x90f10000
#define NVKM_RM_CHAN(chid) (0xf1f00000 | (chid))
#define NVKM_RM_THREED 0x97000000
+#define NVKM_RM_ENGOBJ(class,chid) (((class) << 16) | (chid))
#endif
--
2.49.0
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