[Openchrome-devel] Some HW related questions to VIA:

[BruceChang@via.com.tw]

Hello Thomas:
    Regarding the pixel shader, can I have the detail question you have? After consult with our engineers, it seems we don't have integrated document for it. Everyone seems to have only small piece information.
    For the memory of PM800 / KM400 / K8M800, the architecture of AMD system is different to P4 system. That's why the CPU access difference.

Thanks and Best Regards
Bruce C. Chang

-----Original Message-----
From: Thomas Hellstrom [mailto:thomas at shipmail.org] 
Sent: Sunday, November 09, 2008 10:35 PM
To: Bruce Chang
Cc: Harald Welte; Vincent Tan; Benjamin Pan (Fremont); openchrome-devel at openchrome.org
Subject: Some HW related questions to VIA:


Hi, all

I've got a couple of questions to the VIA engineers. Both VX800 related 
and some related to older hardware:

1) There seems to be no pixel shader language documentation with the 
VX800 docs. Is that something you can release?
2) The VX800 memory types, and how they are programmed. There seems to 
be Local memory which corresponds to VRAM / FB and set up by the bios. 
Also local dynamic memory which seems to be similar to the old AGP 
memory. Is there an aperture to program for this memory or another type 
of  GPU  memory management unit?  Any docs / help on this?
3) PM800 / KM400 /K8M800 Some of these chipsets do not seem able to map 
the framebuffer memory directly which leads to very slow CPU access 
(about 60MB/s or so). On the K8M800 it's possible to figure out how and 
map system memory directly, but it appears like this is not possible on 
the other listed chipsets. Any workaround?
4) K8M800 / KM400. Interrupts seem broken, if they are enabled, the 
device keeps firing a HUGE amount of interrupts. Any workarounds?
5) K8M800 Texturing minification filtering LINEAR_MIPMAP_LINEAR locks 
the device up. A workaround is to use LINEAR_MIPMAP_NEAREST at the 
expense of image quality. Is this a known problem? Any better workarounds?
6) On my P4M890 with dual DDR533 memory,  using the 3D engine causes 
video display controller FIFO underruns. Do we need to change FIFO 
settings when the 3D engine is running?

Any feedback on this would be appreciated.
Thanks,
Thomas Hellstr?m.