[Openchrome-devel] [PATCH] Fix VX900 HDMI port no display issue

[HuangRan]

Remove the write of bit6 for VGA/SVGA CRT Controller Register 0xFD(IGA1
Scaling Up and Timing Control). Bit6 of CRTC 0xFD is RO bit which can
not be written. Verfied on VX900 board for HDMI port.

Signed-off-by: Hu, Yi<huyi at iscas.ac.cn>
Signed-off-by: Huang, Ran<huangranbj at 126.com>
---
 drivers/gpu/drm/via/via_crtc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/via/via_crtc.c b/drivers/gpu/drm/via/via_crtc.c
index fa29270..a50e654 100644
--- a/drivers/gpu/drm/via/via_crtc.c
+++ b/drivers/gpu/drm/via/via_crtc.c
@@ -468,7 +468,7 @@ void via_load_crtc_pixel_timing(struct drm_crtc *crtc, struct drm_display_mode *
 		svga_wcrt_mask(VGABASE, 0x32, 0x00, BIT(2));
 
 	}
-	svga_wcrt_mask(VGABASE, 0xFD, BIT(5) | BIT(6), BIT(5) | BIT(6));
+	svga_wcrt_mask(VGABASE, 0xFD, BIT(5), BIT(5));
 }
 
 /* Load CRTC timing registers */
@@ -484,7 +484,7 @@ void via_load_crtc_timing(struct via_crtc *iga, struct drm_display_mode *mode)
 			svga_wcrt_mask(VGABASE, 0x45, 0x00, BIT(0));
 
 			/* Disable IGA1 pixel timing */
-			svga_wcrt_mask(VGABASE, 0xFD, 0x00, BIT(6) | BIT(5));
+			svga_wcrt_mask(VGABASE, 0xFD, 0x00, BIT(5));
 		}
 
 		reg_value = IGA1_HOR_TOTAL_FORMULA(mode->crtc_htotal);
-- 
1.9.1