[Openchrome-devel] xf86-video-openchrome: 2 commits - configure.ac src/via_display.c src/via_ums.c

[Kevin Brace]

 configure.ac      |    2 +-
 src/via_display.c |   39 +++++++++++++++++++++++++++++++++------
 src/via_ums.c     |    3 ---
 3 files changed, 34 insertions(+), 10 deletions(-)

New commits:
commit 9812c7bc26888fe9a0d4d3e0d8c4fcbbb383d2a7
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Fri Aug 19 23:55:07 2016 -0700

    Version bumped to 0.5.133
    
    This version fixes a potential bug where CRTC registers might not be
    accessible in VX855 and VX900 chipsets. This fix was suggested by
    Patrick Chen of VIA Technologies in December 2011, but no one really
    followed up on it until now.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/configure.ac b/configure.ac
index 4493c31..0ad8361 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
 # Initialize Autoconf
 AC_PREREQ(2.57)
 AC_INIT([xf86-video-openchrome],
-        [0.5.132],
+        [0.5.133],
         [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/openchrome],
         [xf86-video-openchrome])
 
commit 292ff4adfa622335c24480fed69f7ef4474163ce
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Fri Aug 19 23:47:41 2016 -0700

    Handling CRTC register protect bit correctly for VX855 and VX900
    
    According to what Patrick Chen of VIA Technologies wrote in December
    2011, CR47[4] (3X5.47[4]) is now CRTC register protect bit for VX855
    and VX900 chipsets.
    
    Suggested-by: Patrick Chen <PatrickChen at via.com.tw>
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/src/via_display.c b/src/via_display.c
index 9c13cf3..8a54f03 100644
--- a/src/via_display.c
+++ b/src/via_display.c
@@ -580,9 +580,19 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
      *               1: Enable */
     ViaCrtcMask(hwp, 0x36, 0x01, 0x01);
 
-    /* For UniChrome Pro and Chrome9. */
-    if ((pVia->Chipset != VIA_CLE266)
-        && (pVia->Chipset != VIA_KM400)) {
+    switch (pVia->Chipset) {
+    case VIA_CLE266:
+    case VIA_KM400:
+        ViaCrtcMask(hwp, 0x47, 0x00, 0x23);
+        break;
+    case VIA_K8M800:
+    case VIA_PM800:
+    case VIA_P4M800PRO:
+    case VIA_CX700:
+    case VIA_P4M890:
+    case VIA_K8M890:
+    case VIA_P4M900:
+    case VIA_VX800:
         /* 3X5.47[7] - IGA1 Timing Plus 2 VCK
          * 3X5.47[6] - IGA1 Timing Plus 4 VCK
          * 3X5.47[5] - Peep at the PCI-bus
@@ -594,10 +604,27 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
          * 3X5.47[1] - LCD Simultaneous Mode Backdoor Register for
          *             8/9 Dot Clocks
          * 3X5.47[0] - LCD Simultaneous Mode Backdoor Register for
-         *             Clock Select and CRTC Register Protect
-         *
-         */
+         *             Clock Select and CRTC Register Protect */
         ViaCrtcMask(hwp, 0x47, 0x00, 0x23);
+        break;
+    case VIA_VX855:
+    case VIA_VX900:
+        /* 3X5.47[7] - IGA1 Timing Plus 2 VCK
+         * 3X5.47[6] - IGA1 Timing Plus 4 VCK
+         * 3X5.47[5] - Peep at the PCI-bus
+         *             0: Disable
+         *             1: Enable
+         * 3X5.47[4] - CRT Timing Register Protect
+         * 3X5.47[3] - IGA1 Timing Plus 6 VCK
+         * 3X5.47[2] - DACOFF Backdoor Register
+         * 3X5.47[1] - LCD Simultaneous Mode Backdoor Register for
+         *             8/9 Dot Clocks
+         * 3X5.47[0] - LCD Simultaneous Mode Backdoor Register for
+         *             Clock Select */
+        ViaCrtcMask(hwp, 0x47, 0x00, 0x33);
+        break;
+    default:
+        break;
     }
 
     /* 3X5.6B[3] - Simultaneous Display Enable
diff --git a/src/via_ums.c b/src/via_ums.c
index 92b2cb5..4820c3c 100644
--- a/src/via_ums.c
+++ b/src/via_ums.c
@@ -277,9 +277,6 @@ viaMapMMIO(ScrnInfoPtr pScrn)
 
     viaMMIOEnable(pScrn);
 
-    /* Unlock CRTC. */
-    ViaCrtcMask(hwp, 0x47, 0x00, 0x01);
-
     vgaHWGetIOBase(hwp);
 
     DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,