[Openchrome-devel] xf86-video-openchrome: src/via_display.c src/via_outputs.c

[Kevin Brace]

 src/via_display.c |    4 ++--
 src/via_outputs.c |   19 ++++---------------
 2 files changed, 6 insertions(+), 17 deletions(-)

New commits:
commit e7be60ee371affe2e91ba8e8b2ea931e311ad26c
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Mon Feb 8 21:26:02 2016 -0800

    Preserving PCI Burst Write Wait State Select Bit
    
    The code was previously setting PCI Burst Write Wait State Select bit
    (0x3c5.0x1a[2]) to 1 for no good reasons. Typically, the option to enable
    1 wait state PCI transaction in many VIA Technologies chipset-based
    computers is provided in the BIOS setup, therefore, it is prudent for the
    graphics device driver not to alter this bit.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/src/via_display.c b/src/via_display.c
index 4c588c8..0eb8b68 100644
--- a/src/via_display.c
+++ b/src/via_display.c
@@ -324,7 +324,7 @@ ViaFirstCRTCSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode)
             ViaSeqMask(hwp, 0x16, 0x08, 0xBF);
             ViaSeqMask(hwp, 0x17, 0x1F, 0xFF);
             ViaSeqMask(hwp, 0x18, 0x4E, 0xFF);
-            ViaSeqMask(hwp, 0x1A, 0x08, 0xFD);
+            ViaSeqMask(hwp, 0x1A, 0x08, 0xF9);
             break;
     }
 
@@ -594,7 +594,7 @@ ViaSecondCRTCSetMode(ScrnInfoPtr pScrn, DisplayModePtr mode)
             ViaSeqMask(hwp, 0x16, 0x08, 0xBF);
             ViaSeqMask(hwp, 0x17, 0x1F, 0xFF);
             ViaSeqMask(hwp, 0x18, 0x4E, 0xFF);
-            ViaSeqMask(hwp, 0x1A, 0x08, 0xFD);
+            ViaSeqMask(hwp, 0x1A, 0x08, 0xF9);
             break;
     }
 
diff --git a/src/via_outputs.c b/src/via_outputs.c
index 3aa8c97..c661a4f 100644
--- a/src/via_outputs.c
+++ b/src/via_outputs.c
@@ -1404,8 +1404,8 @@ ViaModePrimaryLegacy(xf86CrtcPtr crtc, DisplayModePtr mode)
     pBIOSInfo->Clock = ViaModeDotClockTranslate(pScrn, mode);
     pBIOSInfo->ClockExternal = FALSE;
 
-    /* Enable MMIO & PCI burst (1 wait state) */
-    ViaSeqMask(hwp, 0x1A, 0x06, 0x06);
+    /* Enable Extended Mode Memory Access. */
+    ViaSeqMask(hwp, 0x1A, 0x08, 0x08);
 
     if (pBIOSInfo->analog->status == XF86OutputStatusConnected)
         ViaCrtcMask(hwp, 0x36, 0x30, 0x30);
@@ -1523,19 +1523,8 @@ ViaModeFirstCRTC(ScrnInfoPtr pScrn, DisplayModePtr mode)
     pBIOSInfo->Clock = ViaModeDotClockTranslate(pScrn, mode);
     pBIOSInfo->ClockExternal = FALSE;
 
-    /* Enable MMIO & PCI burst (1 wait state) */
-    switch (pVia->Chipset) {
-        case VIA_CLE266:
-        case VIA_KM400:
-        case VIA_K8M800:
-        case VIA_PM800:
-        case VIA_P4M800PRO:
-            ViaSeqMask(hwp, 0x1A, 0x06, 0x06);
-            break;
-        default:
-            ViaSeqMask(hwp, 0x1A, 0x0C, 0x0C);
-            break;
-    }
+    /* Enable Extended Mode Memory Access. */
+    ViaSeqMask(hwp, 0x1A, 0x08, 0x08);
 
     ViaSetPrimaryFIFO(pScrn, mode);