[Openchrome-devel] xf86-video-openchrome: 2 commits - src/via_display.c

[Kevin Brace]

 src/via_display.c |   27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

New commits:
commit e520ca27dbb769f34c9828f3fb2d36a172b27a0a
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jun 2 03:14:03 2016 -0700

    Cleanup of the code that sets IGA1 vertical synchronization end
    
    viaIGA1SetDisplayRegister function contains the code in question.
    This function is located inside via_display.c.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/src/via_display.c b/src/via_display.c
index 01deed0..b19c0cd 100644
--- a/src/via_display.c
+++ b/src/via_display.c
@@ -860,8 +860,18 @@ viaIGA1SetDisplayRegister(ScrnInfoPtr pScrn, DisplayModePtr mode)
     ViaCrtcMask(hwp, 0x35, temp >> 9, 0x02);
 
 
-    /* vertical sync end : start + 16 -- other bits someplace? */
-    ViaCrtcMask(hwp, 0x11, mode->CrtcVSyncEnd, 0x0F);
+    /* Set IGA1 vertical synchronization end. */
+    /* Vertical synchronization end requires the value to be 1 less
+     * than the actual value being written, and 4 LSB
+     * (Least Significant Bits) are written straight into the
+     * relevant register. */
+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+                        "IGA1 CrtcVSyncEnd: %d\n", mode->CrtcVSyncEnd));
+    temp = mode->CrtcVSyncEnd - 1;
+
+    /*3X5.11[3:0] - Vertical Retrace End Bits [3:0] */
+    ViaCrtcMask(hwp, 0x11, temp & 0x0F, 0x0F);
+
 
     /* line compare: We are not doing splitscreen so 0x3FFF */
     hwp->writeCrtc(hwp, 0x18, 0xFF);
commit c10d8fda63641a16b556812bc6f67a74df03109e
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jun 2 03:00:26 2016 -0700

    Cleanup of the code that sets IGA1 vertical synchronization start
    
    viaIGA1SetDisplayRegister function contains the code in question.
    This function is located inside via_display.c.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/src/via_display.c b/src/via_display.c
index c59bd6a..01deed0 100644
--- a/src/via_display.c
+++ b/src/via_display.c
@@ -842,13 +842,24 @@ viaIGA1SetDisplayRegister(ScrnInfoPtr pScrn, DisplayModePtr mode)
     hwp->writeCrtc(hwp, 0x16, temp & 0xFF);
 
 
-    /* vertical sync start : 2047 */
+    /* Set IGA1 vertical synchronization start. */
+    DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+                        "IGA1 CrtcVSyncStart: %d\n", mode->CrtcVSyncStart));
     temp = mode->CrtcVSyncStart;
+
+    /* 3X5.10[7:0] - Vertical Retrace Start Bits [7:0] */
     hwp->writeCrtc(hwp, 0x10, temp & 0xFF);
+
+    /* 3X5.07[2] - Vertical Retrace Start Bit [8] */
     ViaCrtcMask(hwp, 0x07, temp >> 6, 0x04);
+
+    /* 3X5.07[7] - Vertical Retrace Start Bit [9] */
     ViaCrtcMask(hwp, 0x07, temp >> 2, 0x80);
+
+    /* 3X5.35[1] - Vertical Retrace Start Bit [10] */
     ViaCrtcMask(hwp, 0x35, temp >> 9, 0x02);
 
+
     /* vertical sync end : start + 16 -- other bits someplace? */
     ViaCrtcMask(hwp, 0x11, mode->CrtcVSyncEnd, 0x0F);