[Openchrome-devel] xf86-video-openchrome: 2 commits - configure.ac src/via_display.c src/via_outputs.c src/via_sii164.c src/via_tv.c src/via_ums.h src/via_vt1632.c
Kevin Brace
kevinbrace at kemper.freedesktop.org
Sun Sep 11 06:52:34 UTC 2016
configure.ac | 2
src/via_display.c | 62 +-------------
src/via_outputs.c | 154 ++++++++++++++++++++++++++++++++++++
src/via_sii164.c | 202 +++++++++++++++++++++++++++++++++++++++++++++++
src/via_tv.c | 230 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
src/via_ums.h | 12 ++
src/via_vt1632.c | 202 +++++++++++++++++++++++++++++++++++++++++++++++
7 files changed, 806 insertions(+), 58 deletions(-)
New commits:
commit 22eb39ff3e33ff8f9b59fccc7ff2c329a67b3993
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sat Sep 10 23:43:56 2016 -0700
Version bumped to 0.5.154
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/configure.ac b/configure.ac
index f8bde36..16c34e9 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
# Initialize Autoconf
AC_PREREQ(2.57)
AC_INIT([xf86-video-openchrome],
- [0.5.153],
+ [0.5.154],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/openchrome],
[xf86-video-openchrome])
commit 8932f036cc832982c1aa778237ae2303b8268fab
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sat Sep 10 23:42:07 2016 -0700
Setting I/O driver strength from the relevant code that needs it
The code to set I/O driver strength for clock and data I/O pads
were transferred to the sections where they actually handle the
external device screen mode setting. This affects VIA Technologies
VT1632(A) TMDS transmitter, Silicon Image SiI 164 TMDS transmitter,
and various external TV encoders.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/src/via_display.c b/src/via_display.c
index c8161c8..97e3646 100644
--- a/src/via_display.c
+++ b/src/via_display.c
@@ -605,9 +605,6 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
temp = hwp->readSeq(hwp, 0x1A);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"SR1A: 0x%02X\n", temp));
- temp = hwp->readSeq(hwp, 0x1B);
- DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "SR1B: 0x%02X\n", temp));
temp = hwp->readSeq(hwp, 0x1E);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"SR1E: 0x%02X\n", temp));
@@ -623,9 +620,6 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
temp = hwp->readSeq(hwp, 0x3F);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"SR3F: 0x%02X\n", temp));
- temp = hwp->readSeq(hwp, 0x65);
- DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
- "SR65: 0x%02X\n", temp));
temp = hwp->readCrtc(hwp, 0x36);
DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"CR36: 0x%02X\n", temp));
@@ -725,49 +719,17 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
* Secondary Display’s LUT */
ViaSeqMask(hwp, 0x1A, 0x88, 0xC8);
- /* Set DVP0 data drive strength to 0b11 (highest). */
- /* 3C5.1B[1] - DVP0 Data Drive Strength Bit [0]
- * (It could be for DIP0 (Digital Interface Port 0) for
- * CLE266. Reserved for CX700 / VX700 / VX800 / VX855 /
- * VX900. These newer devices do not have DVP0.) */
- ViaSeqMask(hwp, 0x1B, 0x02, 0x02);
-
- /* Set DVP0 clock drive strength to 0b11 (highest). */
- /* 3C5.1E[7:6] - Video Capture Port Power Control
- * 0x: Pad always off
- * 10: Depend on the other control signal
- * 11: Pad on/off according to the PMS
- * 3C5.1E[5:4] - Digital Video Port 1 Power Control
- * 0x: Pad always off
- * 10: Depend on the other control signal
- * 11: Pad on/off according to the PMS
- * 3C5.1E[3] - Spread Spectrum On/Off
+ /* 3C5.1E[3] - Spread Spectrum On/Off
* 0: Off
* 1: On
- * 3C5.1E[2] - DVP0 Clock Drive Strength Bit [0]
- * (It could be for DIP0 (Digital Interface Port 0) for
- * CLE266. Reserved for CX700 / VX700 / VX800 / VX855 /
- * VX900. These newer devices do not have DVP0.)
* 3C5.1E[1] - Replace ECK by MCK
* For BIST purpose.
* 3C5.1E[0] - On/Off ROC ECK
* 0: Off
* 1: On */
- ViaSeqMask(hwp, 0x1E, 0xF5, 0xFD);
-
- /* Set DVP0 data drive strength to 0b11 (highest). */
- /* Set DVP0 clock drive strength to 0b11 (highest). */
- /* 3C5.2A[7] - Reserved
- * 3C5.2A[6] - The Spread Spectrum Type Control
- * 0: Original Type
- * 1: FIFO Type
- * 3C5.2A[5] - DVP0 Data Drive Strength Bit [1]
- * (Reserved for CX700 / VX700 / VX800 / VX855 /
- * VX900. These devices do not have DVP0.)
- * 3C5.2A[4] - DVP0 Clock Drive Strength Bit [1]
- * (Reserved for CX700 / VX700 / VX800 / VX855 /
- * VX900. These devices do not have DVP0.)
- * 3C5.2A[3:2] - LVDS Channel 2 I/O Pad Control
+ ViaSeqMask(hwp, 0x1E, 0x01, 0x09);
+
+ /* 3C5.2A[3:2] - LVDS Channel 2 I/O Pad Control
* 0x: Pad always off
* 10: Depend on the other control signal
* 11: Pad on/off according to the PMS
@@ -775,7 +737,7 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
* 0x: Pad always off
* 10: Depend on the other control signal
* 11: Pad on/off according to the PMS */
- ViaSeqMask(hwp, 0x2A, 0x3F, 0x3F);
+ ViaSeqMask(hwp, 0x2A, 0x0F, 0x0F);
/* 3C5.2D[7:6] - E3_ECK_N Selection
* 00: E3_ECK_N
@@ -837,20 +799,6 @@ viaIGAInitCommon(ScrnInfoPtr pScrn)
* 11: Clock on/off according to each engine IDLE status */
ViaSeqMask(hwp, 0x3F, 0xFF, 0xFF);
- /* Set DVP1 data drive strength to 0b11 (highest). */
- /* Set DVP1 clock drive strength to 0b11 (highest). */
- /* 3C5.65[3:2] - DVP1 Clock Pads Driving Select
- * 00: lowest
- * 01: low
- * 10: high
- * 11: highest
- * 3C5.65[1:0] - DVP1 Data Pads Driving Select
- * 00: lowest
- * 01: low
- * 10: high
- * 11: highest */
- ViaSeqMask(hwp, 0x65, 0x0F, 0x0F);
-
/* 3X5.36[7] - DPMS VSYNC Output
* 3X5.36[6] - DPMS HSYNC Output
* 3X5.36[5:4] - DPMS Control
diff --git a/src/via_outputs.c b/src/via_outputs.c
index 02978ee..6bd4415 100644
--- a/src/via_outputs.c
+++ b/src/via_outputs.c
@@ -102,6 +102,58 @@ viaDIP0EnableIOPads(ScrnInfoPtr pScrn, CARD8 ioPadState)
}
/*
+ * Sets DIP0 (Digital Interface Port 0) clock I/O pad drive strength
+ * for CLE266 chipset only.
+ */
+void
+viaDIP0SetClockDriveStrength(ScrnInfoPtr pScrn, CARD8 clockDriveStrength)
+{
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaDIP0SetClockDriveStrength.\n"));
+
+ /* 3C5.1E[2] - DIP0 Clock Drive Strength Bit [0] */
+ ViaSeqMask(hwp, 0x1E, clockDriveStrength << 2, 0x04);
+
+ /* 3C5.2A[4] - DIP0 Clock Drive Strength Bit [1] */
+ ViaSeqMask(hwp, 0x2A, clockDriveStrength << 3, 0x10);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "DIP0 Clock I/O Pad Drive Strength: %u\n",
+ clockDriveStrength & 0x03);
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaDIP0SetClockDriveStrength.\n"));
+}
+
+/*
+ * Sets DIP0 (Digital Interface Port 0) data I/O pads drive strength
+ * for CLE266 chipset only.
+ */
+void
+viaDIP0SetDataDriveStrength(ScrnInfoPtr pScrn, CARD8 dataDriveStrength)
+{
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaDIP0SetDataDriveStrength.\n"));
+
+ /* 3C5.1B[1] - DIP0 Data Drive Strength Bit [0] */
+ ViaSeqMask(hwp, 0x1B, dataDriveStrength << 1, 0x02);
+
+ /* 3C5.2A[5] - DIP0 Data Drive Strength Bit [1] */
+ ViaSeqMask(hwp, 0x2A, dataDriveStrength << 4, 0x20);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "DIP0 Data I/O Pads Drive Strength: %u\n",
+ dataDriveStrength);
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaDIP0SetDataDriveStrength.\n"));
+}
+
+/*
* Sets IGA1 or IGA2 as the display output source for DVP0
* (Digital Video Port) interface.
*/
@@ -156,6 +208,56 @@ viaDVP0EnableIOPads(ScrnInfoPtr pScrn, CARD8 ioPadState)
}
/*
+ * Sets DVP0 (Digital Video Port 0) clock I/O pad drive strength.
+ */
+void
+viaDVP0SetClockDriveStrength(ScrnInfoPtr pScrn, CARD8 clockDriveStrength)
+{
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaDVP0SetClockDriveStrength.\n"));
+
+ /* 3C5.1E[2] - DVP0 Clock Drive Strength Bit [0] */
+ ViaSeqMask(hwp, 0x1E, clockDriveStrength << 2, 0x04);
+
+ /* 3C5.2A[4] - DVP0 Clock Drive Strength Bit [1] */
+ ViaSeqMask(hwp, 0x2A, clockDriveStrength << 3, 0x10);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "DVP0 Clock I/O Pad Drive Strength: %u\n",
+ clockDriveStrength & 0x03);
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaDVP0SetClockDriveStrength.\n"));
+}
+
+/*
+ * Sets DVP0 (Digital Video Port 0) data I/O pads drive strength.
+ */
+void
+viaDVP0SetDataDriveStrength(ScrnInfoPtr pScrn, CARD8 dataDriveStrength)
+{
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaDVP0SetDataDriveStrength.\n"));
+
+ /* 3C5.1B[1] - DVP0 Data Drive Strength Bit [0] */
+ ViaSeqMask(hwp, 0x1B, dataDriveStrength << 1, 0x02);
+
+ /* 3C5.2A[5] - DVP0 Data Drive Strength Bit [1] */
+ ViaSeqMask(hwp, 0x2A, dataDriveStrength << 4, 0x20);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "DVP0 Data I/O Pads Drive Strength: %u\n",
+ dataDriveStrength);
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaDVP0SetDataDriveStrength.\n"));
+}
+
+/*
* Sets IGA1 or IGA2 as the display output source for DVP1
* (Digital Video Port) interface.
*/
@@ -210,6 +312,58 @@ viaDVP1EnableIOPads(ScrnInfoPtr pScrn, CARD8 ioPadState)
}
/*
+ * Sets DVP1 (Digital Video Port 1) clock I/O pad drive strength.
+ */
+void
+viaDVP1SetClockDriveStrength(ScrnInfoPtr pScrn, CARD8 clockDriveStrength)
+{
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaDVP1SetClockDriveStrength.\n"));
+
+ /* 3C5.65[3:2] - DVP1 Clock Pads Driving Select
+ * 00: lowest
+ * 01: low
+ * 10: high
+ * 11: highest */
+ ViaSeqMask(hwp, 0x65, clockDriveStrength << 2, 0x0C);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "DVP1 Clock I/O Pad Drive Strength: %u\n",
+ clockDriveStrength & 0x03);
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaDVP1SetClockDriveStrength.\n"));
+}
+
+/*
+ * Sets DVP1 (Digital Video Port 1) data I/O pads drive strength.
+ */
+void
+viaDVP1SetDataDriveStrength(ScrnInfoPtr pScrn, CARD8 dataDriveStrength)
+{
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaDVP1SetDataDriveStrength.\n"));
+
+ /* 3C5.65[1:0] - DVP1 Data Pads Driving Select
+ * 00: lowest
+ * 01: low
+ * 10: high
+ * 11: highest */
+ ViaSeqMask(hwp, 0x65, dataDriveStrength, 0x03);
+
+ xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "DVP1 Data I/O Pads Drive Strength: %u\n",
+ dataDriveStrength & 0x03);
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaDVP1SetDataDriveStrength.\n"));
+}
+
+/*
* Sets IGA1 or IGA2 as the display output source for VIA Technologies
* Chrome IGP DFP (Digital Flat Panel) Low interface.
*/
diff --git a/src/via_sii164.c b/src/via_sii164.c
index 6cbc3c8..c0262da 100644
--- a/src/via_sii164.c
+++ b/src/via_sii164.c
@@ -297,6 +297,206 @@ viaSiI164EnableIOPads(ScrnInfoPtr pScrn, CARD8 ioPadState)
}
static void
+viaSiI164SetClockDriveStrength(ScrnInfoPtr pScrn, CARD8 clockDriveStrength)
+{
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+ VIAPtr pVia = VIAPTR(pScrn);
+ CARD8 sr12, sr13, sr5a;
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaSiI164SetClockDriveStrength.\n"));
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ sr5a = hwp->readSeq(hwp, 0x5A);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR5A: 0x%02X\n", sr5a));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Setting 3C5.5A[0] to 0.\n"));
+ ViaSeqMask(hwp, 0x5A, sr5a & 0xFE, 0x01);
+ }
+
+ sr12 = hwp->readSeq(hwp, 0x12);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR12: 0x%02X\n", sr12));
+ sr13 = hwp->readSeq(hwp, 0x13);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR13: 0x%02X\n", sr13));
+ switch (pVia->Chipset) {
+ case VIA_CLE266:
+ /* 3C5.12[5] - FPD18 pin strapping
+ * 0: DIP0 (Digital Interface Port 0) is used by
+ * a TMDS transmitter (DVI)
+ * 1: DIP0 (Digital Interface Port 0) is used by
+ * a TV encoder */
+ if (!(sr12 & 0x20)) {
+ viaDIP0SetClockDriveStrength(pScrn, clockDriveStrength);
+ }
+
+ break;
+ case VIA_KM400:
+ case VIA_K8M800:
+ case VIA_PM800:
+ case VIA_P4M800PRO:
+ /* 3C5.12[6] - DVP0D6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - DVP0D5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0SetClockDriveStrength(pScrn, clockDriveStrength);
+ }
+
+ break;
+ case VIA_P4M890:
+ case VIA_K8M890:
+ case VIA_P4M900:
+ /* 3C5.12[6] - FPD6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - FPD5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0SetClockDriveStrength(pScrn, clockDriveStrength);
+ }
+
+ break;
+ case VIA_CX700:
+ case VIA_VX800:
+ case VIA_VX855:
+ case VIA_VX900:
+ /* 3C5.13[6] - DVP1 DVP / capture port selection
+ * 0: DVP1 is used as a DVP (Digital Video Port)
+ * 1: DVP1 is used as a capture port */
+ if (!(sr13 & 0x40)) {
+ viaDVP1SetClockDriveStrength(pScrn, clockDriveStrength);
+ }
+
+ break;
+ default:
+ break;
+ }
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ hwp->writeSeq(hwp, 0x5A, sr5a);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Restoring 3C5.5A[0].\n"));
+ }
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaSiI164SetClockDriveStrength.\n"));
+}
+
+static void
+viaSiI164SetDataDriveStrength(ScrnInfoPtr pScrn, CARD8 dataDriveStrength)
+{
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+ VIAPtr pVia = VIAPTR(pScrn);
+ CARD8 sr12, sr13, sr5a;
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaSiI164SetDataDriveStrength.\n"));
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ sr5a = hwp->readSeq(hwp, 0x5A);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR5A: 0x%02X\n", sr5a));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Setting 3C5.5A[0] to 0.\n"));
+ ViaSeqMask(hwp, 0x5A, sr5a & 0xFE, 0x01);
+ }
+
+ sr12 = hwp->readSeq(hwp, 0x12);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR12: 0x%02X\n", sr12));
+ sr13 = hwp->readSeq(hwp, 0x13);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR13: 0x%02X\n", sr13));
+ switch (pVia->Chipset) {
+ case VIA_CLE266:
+ /* 3C5.12[5] - FPD18 pin strapping
+ * 0: DIP0 (Digital Interface Port 0) is used by
+ * a TMDS transmitter (DVI)
+ * 1: DIP0 (Digital Interface Port 0) is used by
+ * a TV encoder */
+ if (!(sr12 & 0x20)) {
+ viaDIP0SetDataDriveStrength(pScrn, dataDriveStrength);
+ }
+
+ break;
+ case VIA_KM400:
+ case VIA_K8M800:
+ case VIA_PM800:
+ case VIA_P4M800PRO:
+ /* 3C5.12[6] - DVP0D6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - DVP0D5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0SetDataDriveStrength(pScrn, dataDriveStrength);
+ }
+
+ break;
+ case VIA_P4M890:
+ case VIA_K8M890:
+ case VIA_P4M900:
+ /* 3C5.12[6] - FPD6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - FPD5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0SetDataDriveStrength(pScrn, dataDriveStrength);
+ }
+
+ break;
+ case VIA_CX700:
+ case VIA_VX800:
+ case VIA_VX855:
+ case VIA_VX900:
+ /* 3C5.13[6] - DVP1 DVP / capture port selection
+ * 0: DVP1 is used as a DVP (Digital Video Port)
+ * 1: DVP1 is used as a capture port */
+ if (!(sr13 & 0x40)) {
+ viaDVP1SetDataDriveStrength(pScrn, dataDriveStrength);
+ }
+
+ break;
+ default:
+ break;
+ }
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ hwp->writeSeq(hwp, 0x5A, sr5a);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Restoring 3C5.5A[0].\n"));
+ }
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaSiI164SetDataDriveStrength.\n"));
+}
+
+static void
via_sii164_dump_registers(ScrnInfoPtr pScrn, I2CDevPtr pDev)
{
int i;
@@ -539,6 +739,8 @@ via_sii164_mode_set(xf86OutputPtr output, DisplayModePtr mode,
viaSiI164SetDisplaySource(pScrn, iga->index ? 0x01 : 0x00);
viaSiI164EnableIOPads(pScrn, 0x03);
+ viaSiI164SetClockDriveStrength(pScrn, 0x03);
+ viaSiI164SetDataDriveStrength(pScrn, 0x03);
via_sii164_dump_registers(pScrn, pSiI164Rec->SiI164I2CDev);
diff --git a/src/via_tv.c b/src/via_tv.c
index 0213964..fd8c9a9 100644
--- a/src/via_tv.c
+++ b/src/via_tv.c
@@ -310,6 +310,232 @@ viaTVEnableIOPads(ScrnInfoPtr pScrn, CARD8 ioPadState)
}
static void
+viaTVSetClockDriveStrength(ScrnInfoPtr pScrn, CARD8 clockDriveStrength)
+{
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+ VIAPtr pVia = VIAPTR(pScrn);
+ CARD8 sr12, sr13, sr5a;
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaTVSetClockDriveStrength.\n"));
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ sr5a = hwp->readSeq(hwp, 0x5A);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR5A: 0x%02X\n", sr5a));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Setting 3C5.5A[0] to 0.\n"));
+ ViaSeqMask(hwp, 0x5A, sr5a & 0xFE, 0x01);
+ }
+
+ sr12 = hwp->readSeq(hwp, 0x12);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR12: 0x%02X\n", sr12));
+ sr13 = hwp->readSeq(hwp, 0x13);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR13: 0x%02X\n", sr13));
+ switch (pVia->Chipset) {
+ case VIA_CLE266:
+ /* 3C5.12[5] - FPD18 pin strapping
+ * 0: DIP0 (Digital Interface Port 0) is used by
+ * a TMDS transmitter (DVI)
+ * 1: DIP0 (Digital Interface Port 0) is used by
+ * a TV encoder */
+ if (sr12 & 0x20) {
+ viaDIP0SetClockDriveStrength(pScrn, clockDriveStrength);
+ }
+
+ break;
+ case VIA_KM400:
+ case VIA_K8M800:
+ case VIA_PM800:
+ case VIA_P4M800PRO:
+ /* 3C5.13[3] - DVP0D8 pin strapping
+ * 0: AGP pins are used for AGP
+ * 1: AGP pins are used by FPDP
+ * (Flat Panel Display Port)
+ * 3C5.12[6] - DVP0D6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - DVP0D5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder
+ * 3C5.12[4] - DVP0D4 pin strapping
+ * 0: Dual 12-bit FPDP (Flat Panel Display Port)
+ * 1: 24-bit FPDP (Flat Panel Display Port) */
+ if ((sr12 & 0x40) && (sr12 & 0x20)) {
+ viaDVP0SetClockDriveStrength(pScrn, clockDriveStrength);
+ } else if ((sr13 & 0x08) && (!(sr12 & 0x10))) {
+ } else if (sr13 & 0x08) {
+ viaDVP1SetClockDriveStrength(pScrn, clockDriveStrength);
+ }
+
+ break;
+ case VIA_P4M890:
+ case VIA_K8M890:
+ case VIA_P4M900:
+ /* 3C5.12[6] - FPD6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - FPD5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder
+ * 3C5.12[4] - FPD4 pin strapping
+ * 0: Dual 12-bit FPDP (Flat Panel Display Port)
+ * 1: 24-bit FPDP (Flat Panel Display Port) */
+ if ((sr12 & 0x40) && (sr12 & 0x20) && (!(sr12 & 0x10))) {
+ viaDVP0SetClockDriveStrength(pScrn, clockDriveStrength);
+ }
+
+ break;
+ case VIA_CX700:
+ case VIA_VX800:
+ case VIA_VX855:
+ case VIA_VX900:
+ /* 3C5.13[6] - DVP1 DVP / capture port selection
+ * 0: DVP1 is used as a DVP (Digital Video Port)
+ * 1: DVP1 is used as a capture port */
+ if (!(sr13 & 0x40)) {
+ viaDVP1SetClockDriveStrength(pScrn, clockDriveStrength);
+ }
+
+ break;
+ default:
+ break;
+ }
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ hwp->writeSeq(hwp, 0x5A, sr5a);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Restoring 3C5.5A[0].\n"));
+ }
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaTVSetClockDriveStrength.\n"));
+}
+
+static void
+viaTVSetDataDriveStrength(ScrnInfoPtr pScrn, CARD8 dataDriveStrength)
+{
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+ VIAPtr pVia = VIAPTR(pScrn);
+ CARD8 sr12, sr13, sr5a;
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaTVSetDataDriveStrength.\n"));
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ sr5a = hwp->readSeq(hwp, 0x5A);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR5A: 0x%02X\n", sr5a));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Setting 3C5.5A[0] to 0.\n"));
+ ViaSeqMask(hwp, 0x5A, sr5a & 0xFE, 0x01);
+ }
+
+ sr12 = hwp->readSeq(hwp, 0x12);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR12: 0x%02X\n", sr12));
+ sr13 = hwp->readSeq(hwp, 0x13);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR13: 0x%02X\n", sr13));
+ switch (pVia->Chipset) {
+ case VIA_CLE266:
+ /* 3C5.12[5] - FPD18 pin strapping
+ * 0: DIP0 (Digital Interface Port 0) is used by
+ * a TMDS transmitter (DVI)
+ * 1: DIP0 (Digital Interface Port 0) is used by
+ * a TV encoder */
+ if (sr12 & 0x20) {
+ viaDIP0SetDataDriveStrength(pScrn, dataDriveStrength);
+ }
+
+ break;
+ case VIA_KM400:
+ case VIA_K8M800:
+ case VIA_PM800:
+ case VIA_P4M800PRO:
+ /* 3C5.13[3] - DVP0D8 pin strapping
+ * 0: AGP pins are used for AGP
+ * 1: AGP pins are used by FPDP
+ * (Flat Panel Display Port)
+ * 3C5.12[6] - DVP0D6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - DVP0D5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder
+ * 3C5.12[4] - DVP0D4 pin strapping
+ * 0: Dual 12-bit FPDP (Flat Panel Display Port)
+ * 1: 24-bit FPDP (Flat Panel Display Port) */
+ if ((sr12 & 0x40) && (sr12 & 0x20)) {
+ viaDVP0SetDataDriveStrength(pScrn, dataDriveStrength);
+ } else if ((sr13 & 0x08) && (!(sr12 & 0x10))) {
+ } else if (sr13 & 0x08) {
+ viaDVP1SetDataDriveStrength(pScrn, dataDriveStrength);
+ }
+
+ break;
+ case VIA_P4M890:
+ case VIA_K8M890:
+ case VIA_P4M900:
+ /* 3C5.12[6] - FPD6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - FPD5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder
+ * 3C5.12[4] - FPD4 pin strapping
+ * 0: Dual 12-bit FPDP (Flat Panel Display Port)
+ * 1: 24-bit FPDP (Flat Panel Display Port) */
+ if ((sr12 & 0x40) && (sr12 & 0x20) && (!(sr12 & 0x10))) {
+ viaDVP0SetDataDriveStrength(pScrn, dataDriveStrength);
+ }
+
+ break;
+ case VIA_CX700:
+ case VIA_VX800:
+ case VIA_VX855:
+ case VIA_VX900:
+ /* 3C5.13[6] - DVP1 DVP / capture port selection
+ * 0: DVP1 is used as a DVP (Digital Video Port)
+ * 1: DVP1 is used as a capture port */
+ if (!(sr13 & 0x40)) {
+ viaDVP1SetDataDriveStrength(pScrn, dataDriveStrength);
+ }
+
+ break;
+ default:
+ break;
+ }
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ hwp->writeSeq(hwp, 0x5A, sr5a);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Restoring 3C5.5A[0].\n"));
+ }
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaTVSetDataDriveStrength.\n"));
+}
+
+static void
ViaTVSave(ScrnInfoPtr pScrn)
{
VIABIOSInfoPtr pBIOSInfo = VIAPTR(pScrn)->pBIOSInfo;
@@ -481,6 +707,10 @@ via_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
/* Set I/O pads to automatic on / off mode. */
viaTVEnableIOPads(pScrn, 0x03);
+
+ viaTVSetClockDriveStrength(pScrn, 0x03);
+ viaTVSetDataDriveStrength(pScrn, 0x03);
+
ViaTVSetMode(output->crtc, adjusted_mode);
}
diff --git a/src/via_ums.h b/src/via_ums.h
index d04d90a..60a72e9 100644
--- a/src/via_ums.h
+++ b/src/via_ums.h
@@ -211,10 +211,22 @@ Bool umsCrtcInit(ScrnInfoPtr pScrn);
/* via_output.c */
void viaDIP0SetDisplaySource(ScrnInfoPtr pScrn, CARD8 displaySource);
void viaDIP0EnableIOPads(ScrnInfoPtr pScrn, CARD8 ioPadState);
+void viaDIP0SetClockDriveStrength(ScrnInfoPtr pScrn,
+ CARD8 clockDriveStrength);
+void viaDIP0SetDataDriveStrength(ScrnInfoPtr pScrn,
+ CARD8 dataDriveStrength);
void viaDVP0SetDisplaySource(ScrnInfoPtr pScrn, CARD8 displaySource);
void viaDVP0EnableIOPads(ScrnInfoPtr pScrn, CARD8 ioPadState);
+void viaDVP0SetClockDriveStrength(ScrnInfoPtr pScrn,
+ CARD8 clockDriveStrength);
+void viaDVP0SetDataDriveStrength(ScrnInfoPtr pScrn,
+ CARD8 dataDriveStrength);
void viaDVP1SetDisplaySource(ScrnInfoPtr pScrn, CARD8 displaySource);
void viaDVP1EnableIOPads(ScrnInfoPtr pScrn, CARD8 ioPadState);
+void viaDVP1SetClockDriveStrength(ScrnInfoPtr pScrn,
+ CARD8 clockDriveStrength);
+void viaDVP1SetDataDriveStrength(ScrnInfoPtr pScrn,
+ CARD8 dataDriveStrength);
void viaDFPLowSetDisplaySource(ScrnInfoPtr pScrn, CARD8 displaySource);
void viaDFPLowEnableIOPads(ScrnInfoPtr pScrn, CARD8 ioPadState);
void viaOutputDetect(ScrnInfoPtr pScrn);
diff --git a/src/via_vt1632.c b/src/via_vt1632.c
index 6fb126c..81559a7 100644
--- a/src/via_vt1632.c
+++ b/src/via_vt1632.c
@@ -297,6 +297,206 @@ viaVT1632EnableIOPads(ScrnInfoPtr pScrn, CARD8 ioPadState)
}
static void
+viaVT1632SetClockDriveStrength(ScrnInfoPtr pScrn, CARD8 clockDriveStrength)
+{
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+ VIAPtr pVia = VIAPTR(pScrn);
+ CARD8 sr12, sr13, sr5a;
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaVT1632SetClockDriveStrength.\n"));
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ sr5a = hwp->readSeq(hwp, 0x5A);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR5A: 0x%02X\n", sr5a));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Setting 3C5.5A[0] to 0.\n"));
+ ViaSeqMask(hwp, 0x5A, sr5a & 0xFE, 0x01);
+ }
+
+ sr12 = hwp->readSeq(hwp, 0x12);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR12: 0x%02X\n", sr12));
+ sr13 = hwp->readSeq(hwp, 0x13);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR13: 0x%02X\n", sr13));
+ switch (pVia->Chipset) {
+ case VIA_CLE266:
+ /* 3C5.12[5] - FPD18 pin strapping
+ * 0: DIP0 (Digital Interface Port 0) is used by
+ * a TMDS transmitter (DVI)
+ * 1: DIP0 (Digital Interface Port 0) is used by
+ * a TV encoder */
+ if (!(sr12 & 0x20)) {
+ viaDIP0SetClockDriveStrength(pScrn, clockDriveStrength);
+ }
+
+ break;
+ case VIA_KM400:
+ case VIA_K8M800:
+ case VIA_PM800:
+ case VIA_P4M800PRO:
+ /* 3C5.12[6] - DVP0D6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - DVP0D5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0SetClockDriveStrength(pScrn, clockDriveStrength);
+ }
+
+ break;
+ case VIA_P4M890:
+ case VIA_K8M890:
+ case VIA_P4M900:
+ /* 3C5.12[6] - FPD6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - FPD5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0SetClockDriveStrength(pScrn, clockDriveStrength);
+ }
+
+ break;
+ case VIA_CX700:
+ case VIA_VX800:
+ case VIA_VX855:
+ case VIA_VX900:
+ /* 3C5.13[6] - DVP1 DVP / capture port selection
+ * 0: DVP1 is used as a DVP (Digital Video Port)
+ * 1: DVP1 is used as a capture port */
+ if (!(sr13 & 0x40)) {
+ viaDVP1SetClockDriveStrength(pScrn, clockDriveStrength);
+ }
+
+ break;
+ default:
+ break;
+ }
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ hwp->writeSeq(hwp, 0x5A, sr5a);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Restoring 3C5.5A[0].\n"));
+ }
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaVT1632SetClockDriveStrength.\n"));
+}
+
+static void
+viaVT1632SetDataDriveStrength(ScrnInfoPtr pScrn, CARD8 dataDriveStrength)
+{
+ vgaHWPtr hwp = VGAHWPTR(pScrn);
+ VIAPtr pVia = VIAPTR(pScrn);
+ CARD8 sr12, sr13, sr5a;
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Entered viaVT1632SetDataDriveStrength.\n"));
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ sr5a = hwp->readSeq(hwp, 0x5A);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR5A: 0x%02X\n", sr5a));
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Setting 3C5.5A[0] to 0.\n"));
+ ViaSeqMask(hwp, 0x5A, sr5a & 0xFE, 0x01);
+ }
+
+ sr12 = hwp->readSeq(hwp, 0x12);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR12: 0x%02X\n", sr12));
+ sr13 = hwp->readSeq(hwp, 0x13);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "SR13: 0x%02X\n", sr13));
+ switch (pVia->Chipset) {
+ case VIA_CLE266:
+ /* 3C5.12[5] - FPD18 pin strapping
+ * 0: DIP0 (Digital Interface Port 0) is used by
+ * a TMDS transmitter (DVI)
+ * 1: DIP0 (Digital Interface Port 0) is used by
+ * a TV encoder */
+ if (!(sr12 & 0x20)) {
+ viaDIP0SetDataDriveStrength(pScrn, dataDriveStrength);
+ }
+
+ break;
+ case VIA_KM400:
+ case VIA_K8M800:
+ case VIA_PM800:
+ case VIA_P4M800PRO:
+ /* 3C5.12[6] - DVP0D6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - DVP0D5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0SetDataDriveStrength(pScrn, dataDriveStrength);
+ }
+
+ break;
+ case VIA_P4M890:
+ case VIA_K8M890:
+ case VIA_P4M900:
+ /* 3C5.12[6] - FPD6 pin strapping
+ * 0: Disable DVP0 (Digital Video Port 0)
+ * 1: Enable DVP0 (Digital Video Port 0)
+ * 3C5.12[5] - FPD5 pin strapping
+ * 0: DVP0 is used by a TMDS transmitter (DVI)
+ * 1: DVP0 is used by a TV encoder */
+ if ((sr12 & 0x40) && (!(sr12 & 0x20))) {
+ viaDVP0SetDataDriveStrength(pScrn, dataDriveStrength);
+ }
+
+ break;
+ case VIA_CX700:
+ case VIA_VX800:
+ case VIA_VX855:
+ case VIA_VX900:
+ /* 3C5.13[6] - DVP1 DVP / capture port selection
+ * 0: DVP1 is used as a DVP (Digital Video Port)
+ * 1: DVP1 is used as a capture port */
+ if (!(sr13 & 0x40)) {
+ viaDVP1SetDataDriveStrength(pScrn, dataDriveStrength);
+ }
+
+ break;
+ default:
+ break;
+ }
+
+ if ((pVia->Chipset == VIA_CX700)
+ || (pVia->Chipset == VIA_VX800)
+ || (pVia->Chipset == VIA_VX855)
+ || (pVia->Chipset == VIA_VX900)) {
+
+ hwp->writeSeq(hwp, 0x5A, sr5a);
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Restoring 3C5.5A[0].\n"));
+ }
+
+ DEBUG(xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+ "Exiting viaVT1632SetDataDriveStrength.\n"));
+}
+
+static void
via_vt1632_dump_registers(ScrnInfoPtr pScrn, I2CDevPtr pDev)
{
int i;
@@ -552,6 +752,8 @@ via_vt1632_mode_set(xf86OutputPtr output, DisplayModePtr mode,
viaVT1632SetDisplaySource(pScrn, iga->index ? 0x01 : 0x00);
viaVT1632EnableIOPads(pScrn, 0x03);
+ viaVT1632SetClockDriveStrength(pScrn, 0x03);
+ viaVT1632SetDataDriveStrength(pScrn, 0x03);
via_vt1632_dump_registers(pScrn, pVIAVT1632Rec->VT1632I2CDev);
More information about the Openchrome-devel
mailing list