[Openchrome-devel] drm-openchrome: Branch 'drm-next-3.19' - 2 commits - drivers/gpu/drm

Kevin Brace kevinbrace at kemper.freedesktop.org
Tue Dec 19 07:44:45 UTC 2017


 drivers/gpu/drm/openchrome/via_crtc.c |   81 ++++++++++++++++++++--------------
 drivers/gpu/drm/openchrome/via_drv.h  |    4 -
 2 files changed, 51 insertions(+), 34 deletions(-)

New commits:
commit 6b81833e48d921b6df243f839f63367ad92e2f3b
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Tue Dec 19 01:43:57 2017 -0600

    drm/openchrome: Version bumped to 3.0.64
    
    More fixes for CLE266 and KM400 chipsets.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/openchrome/via_drv.h b/drivers/gpu/drm/openchrome/via_drv.h
index 1933c446f0b9..e037e347f8c2 100644
--- a/drivers/gpu/drm/openchrome/via_drv.h
+++ b/drivers/gpu/drm/openchrome/via_drv.h
@@ -30,11 +30,11 @@
 #define DRIVER_AUTHOR       "OpenChrome Project"
 #define DRIVER_NAME         "openchrome"
 #define DRIVER_DESC         "OpenChrome DRM for VIA Technologies Chrome IGP"
-#define DRIVER_DATE         "20171218"
+#define DRIVER_DATE         "20171219"
 
 #define DRIVER_MAJOR		3
 #define DRIVER_MINOR		0
-#define DRIVER_PATCHLEVEL	63
+#define DRIVER_PATCHLEVEL	64
 
 #include <linux/module.h>
 
commit 38fdf80002241aa820f47562017bd919a6cb2b55
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Tue Dec 19 01:41:10 2017 -0600

    drm/openchrome: Simplify extended display FIFO control code
    
    This is for CLE266 and KM400 chipsets.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/openchrome/via_crtc.c b/drivers/gpu/drm/openchrome/via_crtc.c
index 33e55af082b8..57d2fac2f6f0 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -486,6 +486,7 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
                                         struct drm_framebuffer *fb)
 {
     u32 reg_value;
+    bool enable_extended_display_fifo = false;
 
     DRM_DEBUG_KMS("Entered %s.\n", __func__);
 
@@ -501,6 +502,8 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
 
                 /* SR18[5:0] */
                 iga->fifo_high_threshold = 92;
+
+                enable_extended_display_fifo = true;
             } else {
                 /* SR17[6:0] */
                 iga->fifo_max_depth = 128;
@@ -510,6 +513,8 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
 
                 /* SR18[5:0] */
                 iga->fifo_high_threshold = 56;
+
+                enable_extended_display_fifo = false;
             }
 
             if (dev_priv->vram_type <= VIA_MEM_DDR_200) {
@@ -564,6 +569,8 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
 
                 /* SR18[5:0] */
                 iga->fifo_high_threshold = 92;
+
+                enable_extended_display_fifo = false;
             } else {
                 /* SR17[6:0] */
                 iga->fifo_max_depth = 128;
@@ -573,6 +580,8 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
 
                 /* SR18[5:0] */
                 iga->fifo_high_threshold = 56;
+
+                enable_extended_display_fifo = false;
             }
 
             if (dev_priv->vram_type <= VIA_MEM_DDR_200) {
@@ -602,6 +611,7 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
             }
         }
         break;
+
     case PCI_DEVICE_ID_VIA_KM400:
         if ((mode->hdisplay >= 1600) &&
             (dev_priv->vram_type <= VIA_MEM_DDR_200)) {
@@ -624,6 +634,8 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
             iga->fifo_high_threshold = 92;
         }
 
+        enable_extended_display_fifo = false;
+
         if (dev_priv->vram_type <= VIA_MEM_DDR_200) {
             if (mode->hdisplay >= 1600) {
                 /* SR22[4:0] */
@@ -716,20 +728,29 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
         (dev->pdev->device == PCI_DEVICE_ID_VIA_KM400)) {
         /* Force PREQ to be always higer than TREQ. */
         svga_wseq_mask(VGABASE, 0x18, BIT(6), BIT(6));
-    }
 
-    if ((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) &&
-        (dev_priv->revision == CLE266_REVISION_AX) &&
-        (mode->hdisplay > 1024)) {
-        reg_value = VIA_READ(0x0298);
-        VIA_WRITE(0x0298, reg_value | 0x20000000);
+        if (enable_extended_display_fifo) {
+            reg_value = VIA_READ(0x0298);
+            VIA_WRITE(0x0298, reg_value | 0x20000000);
 
-        /* Turn on IGA1 extended display FIFO. */
-        reg_value = VIA_READ(0x0230);
-        VIA_WRITE(0x0230, reg_value | 0x00200000);
+            /* Turn on IGA1 extended display FIFO. */
+            reg_value = VIA_READ(0x0230);
+            VIA_WRITE(0x0230, reg_value | 0x00200000);
 
-        reg_value = VIA_READ(0x0298);
-        VIA_WRITE(0x0298, reg_value & (~0x20000000));
+            reg_value = VIA_READ(0x0298);
+            VIA_WRITE(0x0298, reg_value & (~0x20000000));
+        } else {
+            reg_value = VIA_READ(0x0298);
+            VIA_WRITE(0x0298, reg_value | 0x20000000);
+
+            /* Turn off IGA1 extended display FIFO. */
+            reg_value = VIA_READ(0x0230);
+            VIA_WRITE(0x0230, reg_value & (~0x00200000));
+
+            reg_value = VIA_READ(0x0298);
+            VIA_WRITE(0x0298, reg_value & (~0x20000000));
+
+        }
     }
 
     /* If resolution > 1280x1024, expire length = 64, else
@@ -765,6 +786,7 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
                                         struct drm_framebuffer *fb)
 {
     u32 reg_value;
+    bool enable_extended_display_fifo = false;
 
     DRM_DEBUG_KMS("Entered %s.\n", __func__);
 
@@ -782,12 +804,16 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
 
                 /* CR68[3:0] */
                 iga->fifo_threshold = 44;
+
+                enable_extended_display_fifo = true;
             } else {
                 /* CR68[7:4] */
                 iga->fifo_max_depth = 56;
 
                 /* CR68[3:0] */
                 iga->fifo_threshold = 28;
+
+                enable_extended_display_fifo = false;
             }
         /* dev_priv->revision == CLE266_REVISION_CX */
         } else {
@@ -797,12 +823,16 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
 
                 /* CR68[3:0] */
                 iga->fifo_threshold = 44;
+
+                enable_extended_display_fifo = false;
             } else {
                 /* CR68[7:4] */
                 iga->fifo_max_depth = 56;
 
                 /* CR68[3:0] */
                 iga->fifo_threshold = 28;
+
+                enable_extended_display_fifo = false;
             }
         }
 
@@ -815,8 +845,7 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
             /* CR68[3:0] */
             iga->fifo_threshold = 44;
 
-            /* Enable IGA2 extended display FIFO. */
-            svga_wcrt_mask(VGABASE, 0x6a, BIT(5), BIT(5));
+            enable_extended_display_fifo = true;
         } else if (((mode->hdisplay > 1024) &&
                         (fb->bits_per_pixel == 32) &&
                         (dev_priv->vram_type <= VIA_MEM_DDR_333))
@@ -829,8 +858,7 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
             /* CR68[3:0] */
             iga->fifo_threshold = 28;
 
-            /* Enable IGA2 extended display FIFO. */
-            svga_wcrt_mask(VGABASE, 0x6a, BIT(5), BIT(5));
+            enable_extended_display_fifo = true;
         } else if (((mode->hdisplay > 1280) &&
                         (fb->bits_per_pixel == 16) &&
                         (dev_priv->vram_type <= VIA_MEM_DDR_333))
@@ -843,8 +871,7 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
             /* CR68[3:0] */
             iga->fifo_threshold = 44;
 
-            /* Enable IGA2 extended display FIFO. */
-            svga_wcrt_mask(VGABASE, 0x6a, BIT(5), BIT(5));
+            enable_extended_display_fifo = true;
         } else {
             /* CR68[7:4] */
             iga->fifo_max_depth = 56;
@@ -852,8 +879,7 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
             /* CR68[3:0] */
             iga->fifo_threshold = 28;
 
-            /* Disable IGA2 extended display FIFO. */
-            svga_wcrt_mask(VGABASE, 0x6a, 0x00, BIT(5));
+            enable_extended_display_fifo = false;
         }
 
         break;
@@ -938,26 +964,17 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
 
     if ((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) ||
         (dev->pdev->device == PCI_DEVICE_ID_VIA_KM400)) {
-        if (((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) &&
-                (dev_priv->revision == CLE266_REVISION_AX) &&
-                (dev_priv->vram_type <= VIA_MEM_DDR_200) &&
-                (fb->bits_per_pixel > 16) &&
-                (mode->vdisplay > 768))
-            || ((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) &&
-                (dev_priv->revision == CLE266_REVISION_AX) &&
-                (dev_priv->vram_type <= VIA_MEM_DDR_266) &&
-                (fb->bits_per_pixel > 16) &&
-                (mode->hdisplay > 1280))
-            || ((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) &&
-                (dev_priv->revision == CLE266_REVISION_CX) &&
-                (mode->hdisplay >= 1024))) {
+        if (enable_extended_display_fifo) {
             /* Enable IGA2 extended display FIFO. */
             svga_wcrt_mask(VGABASE, 0x6a, BIT(5), BIT(5));
         } else {
             /* Disable IGA2 extended display FIFO. */
             svga_wcrt_mask(VGABASE, 0x6a, 0x00, BIT(5));
         }
+    }
 
+    if ((dev->pdev->device == PCI_DEVICE_ID_VIA_CLE266) ||
+        (dev->pdev->device == PCI_DEVICE_ID_VIA_KM400)) {
         /* Set IGA2 Display FIFO Depth Select */
         reg_value = IGA2_FIFO_DEPTH_SELECT_FORMULA(iga->fifo_max_depth);
         load_value_to_registers(VGABASE, &iga->fifo_depth, reg_value);


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