[Openchrome-devel] xf86-video-openchrome: 2 commits - configure.ac src/via_display.c

[Kevin Brace]

 configure.ac      |    2 +-
 src/via_display.c |   30 ++++++++++++++++++++++++++++++
 2 files changed, 31 insertions(+), 1 deletion(-)

New commits:
commit 9f70120874e48987baa62ce2ffd8f1a83b9a8194
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Sat Feb 25 14:42:42 2017 -0800

    Version bumped to 0.5.186
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/configure.ac b/configure.ac
index 9317f1b..7db0b45 100644
--- a/configure.ac
+++ b/configure.ac
@@ -23,7 +23,7 @@
 # Initialize Autoconf
 AC_PREREQ(2.57)
 AC_INIT([xf86-video-openchrome],
-        [0.5.185],
+        [0.5.186],
         [https://bugs.freedesktop.org/enter_bug.cgi?product=xorg&component=Driver/openchrome],
         [xf86-video-openchrome])
 
commit e2c3873e05d483141ac8c2258ec7b4d427db9882
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Sat Feb 25 14:24:19 2017 -0800

    Checking display controller memory alignment before mode setting
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/src/via_display.c b/src/via_display.c
index b04bfe9..bdf8fc6 100644
--- a/src/via_display.c
+++ b/src/via_display.c
@@ -3707,6 +3707,21 @@ iga1_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
                     (unsigned)temp, (unsigned)pVia->pBIOSInfo->Bandwidth);
         return FALSE;
     }
+
+    if (!pScrn->bitsPerPixel) {
+        xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+                    "Invalid bpp information.\n");
+        return FALSE;
+    }
+
+    /* 16 is the Chrome IGP display controller memory alignment. */
+    if (crtc->x % (16 / ((pScrn->bitsPerPixel + 7) >> 3))) {
+        xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+                    "The X location specified is not properly aligned "
+                    "to Chrome IGP's memory alignment.\n");
+        return FALSE;
+    }
+
     return TRUE;
 }
 
@@ -4108,6 +4123,21 @@ iga2_crtc_mode_fixup(xf86CrtcPtr crtc, DisplayModePtr mode,
                     (unsigned)temp, (unsigned)pVia->pBIOSInfo->Bandwidth);
         return FALSE;
     }
+
+    if (!pScrn->bitsPerPixel) {
+        xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+                    "Invalid bpp information.\n");
+        return FALSE;
+    }
+
+    /* 16 is the Chrome IGP display controller memory alignment. */
+    if (crtc->x % (16 / ((pScrn->bitsPerPixel + 7) >> 3))) {
+        xf86DrvMsg(pScrn->scrnIndex, X_INFO,
+                    "The X location specified is not properly aligned "
+                    "to Chrome IGP's memory alignment.\n");
+        return FALSE;
+    }
+
     return TRUE;
 }