[Openchrome-devel] drm-openchrome: 27 commits - drivers/gpu/drm

Kevin Brace kevinbrace at kemper.freedesktop.org
Fri Jul 7 04:54:24 UTC 2017


 drivers/gpu/drm/via/crtc_hw.h |  470 +++++++++++++++++++++++++++++++++++++-----
 drivers/gpu/drm/via/via_drv.h |    4 
 drivers/gpu/drm/via/via_fp.c  |   54 ++++
 3 files changed, 470 insertions(+), 58 deletions(-)

New commits:
commit d027a777154a1cc3c57ad2af9690851ebe593a76
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 23:52:51 2017 -0500

    Version bumped to 3.0.39
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/via_drv.h b/drivers/gpu/drm/via/via_drv.h
index 079f4405c8d..47d2ac2c504 100644
--- a/drivers/gpu/drm/via/via_drv.h
+++ b/drivers/gpu/drm/via/via_drv.h
@@ -30,11 +30,11 @@
 #define DRIVER_AUTHOR       "The OpenChrome Project"
 #define DRIVER_NAME         "via"
 #define DRIVER_DESC         "OpenChrome DRM for VIA Technologies Chrome IGP"
-#define DRIVER_DATE         "20170704"
+#define DRIVER_DATE         "20170706"
 
 #define DRIVER_MAJOR		3
 #define DRIVER_MINOR		0
-#define DRIVER_PATCHLEVEL	38
+#define DRIVER_PATCHLEVEL	39
 
 #include <linux/module.h>
 
commit 83a56b58befd72087fe1c9568f5f637e5b933004
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 23:50:55 2017 -0500

    Added via_fp_set_secondary_hard_power
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index 5f578e45811..9224df16868 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -556,6 +556,22 @@ via_fp_set_secondary_direct_display_period(void __iomem *regs,
 }
 
 /*
+ * Sets FP secondary hardware controlled power sequence enable.
+ */
+static inline void
+via_fp_set_secondary_hard_power(void __iomem *regs,
+				bool power_state)
+{
+	/* 3X5.D4[1] - Secondary Power Hardware Power Sequence Enable
+	 *             0: Off
+	 *             1: On */
+	svga_wcrt_mask(regs, 0xD4,
+			power_state ? BIT(1) : 0x00, BIT(1));
+	DRM_DEBUG_KMS("FP Secondary Hardware Controlled Power "
+			"Sequence: %s\n", power_state ? "On" : "Off");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit ea9544d56d005c4d7ff2a073403b9612c3460480
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 23:45:26 2017 -0500

    Added via_fp_set_secondary_direct_display_period
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index 4becfc8350a..5f578e45811 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -539,6 +539,23 @@ via_fp_set_secondary_direct_back_light_ctrl(void __iomem *regs,
 }
 
 /*
+ * Sets CX700 / VX700 or later chipset's FP secondary direct
+ * display period control.
+ */
+static inline void
+via_fp_set_secondary_direct_display_period(void __iomem *regs,
+						bool direct_on)
+{
+	/* 3X5.D3[7] - FP Secondary Direct Display Period Control
+	 *             0: On
+	 *             1: Off */
+	svga_wcrt_mask(regs, 0xD3,
+			direct_on ? 0x00 : BIT(7), BIT(7));
+	DRM_DEBUG_KMS("FP Secondary Direct Display Period "
+			"Control: %s\n", direct_on ? "On" : "Off");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit 508159caae82f03d5fa25622ea88a8be8eda1530
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 23:40:58 2017 -0500

    Added via_fp_set_secondary_direct_back_light_ctrl
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index 20124afbcba..4becfc8350a 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -522,6 +522,23 @@ via_fp_set_secondary_soft_vdd(void __iomem *regs,
 }
 
 /*
+ * Sets CX700 / VX700 or later chipset's FP secondary direct back
+ * light control.
+ */
+static inline void
+via_fp_set_secondary_direct_back_light_ctrl(void __iomem *regs,
+						bool direct_on)
+{
+	/* 3X5.D3[6] - FP Secondary Direct Back Light Control
+	 *             0: On
+	 *             1: Off */
+	svga_wcrt_mask(regs, 0xD3,
+			direct_on ? 0x00 : BIT(6), BIT(6));
+	DRM_DEBUG_KMS("FP Secondary Direct Back Light "
+			"Control: %s\n", direct_on ? "On" : "Off");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit 290ffd0937ae88f3963d70f908a20c4666f62822
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 23:34:05 2017 -0500

    Added via_fp_set_secondary_soft_vdd
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index 2fbce928b12..20124afbcba 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -505,6 +505,23 @@ via_fp_set_secondary_soft_data(void __iomem *regs,
 }
 
 /*
+ * Sets CX700 / VX700 or later chipset's FP secondary software
+ * controlled VDD.
+ */
+static inline void
+via_fp_set_secondary_soft_vdd(void __iomem *regs,
+				bool soft_on)
+{
+	/* 3X5.D3[4] - FP Secondary Software VDD On
+	 *             0: Off
+	 *             1: On */
+	svga_wcrt_mask(regs, 0xD3,
+			soft_on ? BIT(4) : 0x00, BIT(4));
+	DRM_DEBUG_KMS("FP Secondary Software Controlled VDD: %s\n",
+			soft_on ? "On" : "Off");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit 1a93d3777b05cbca9d5bb4e18c15da9b0b289758
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 23:28:50 2017 -0500

    Added via_fp_set_secondary_soft_data
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index 0241f66f491..2fbce928b12 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -488,6 +488,23 @@ via_fp_set_secondary_soft_vee(void __iomem *regs,
 }
 
 /*
+ * Sets CX700 / VX700 or later chipset's FP secondary software
+ * controlled data.
+ */
+static inline void
+via_fp_set_secondary_soft_data(void __iomem *regs,
+				bool soft_on)
+{
+	/* 3X5.D3[3] - FP Secondary Software Data On
+	 *             0: Off
+	 *             1: On */
+	svga_wcrt_mask(regs, 0xD3,
+			soft_on ? BIT(3) : 0x00, BIT(3));
+	DRM_DEBUG_KMS("FP Secondary Software Controlled Data: %s\n",
+			soft_on ? "On" : "Off");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit dd25e5954b8283cc81f659cdbc492c540e2dd2de
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 23:24:02 2017 -0500

    Added via_fp_set_secondary_soft_vee
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index 9e411cc4220..0241f66f491 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -471,6 +471,23 @@ via_fp_set_secondary_soft_back_light(void __iomem *regs,
 }
 
 /*
+ * Sets CX700 / VX700 or later chipset's FP secondary software
+ * controlled VEE.
+ */
+static inline void
+via_fp_set_secondary_soft_vee(void __iomem *regs,
+				bool soft_on)
+{
+	/* 3X5.D3[2] - FP Secondary Software VEE On
+	 *             0: Off
+	 *             1: On */
+	svga_wcrt_mask(regs, 0xD3,
+			soft_on ? BIT(2) : 0x00, BIT(2));
+	DRM_DEBUG_KMS("FP Secondary Software Controlled VEE: %s\n",
+			soft_on ? "On" : "Off");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit 1010e0fc75cd1bc152de0a9b01d0e4d8f83d67f4
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 23:17:20 2017 -0500

    Added via_fp_set_secondary_soft_back_light
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index 0e7850e317e..9e411cc4220 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -454,6 +454,23 @@ via_fp_set_secondary_power_seq_type(void __iomem *regs,
 }
 
 /*
+ * Sets CX700 / VX700 or later chipset's FP secondary
+ * software controlled back light.
+ */
+static inline void
+via_fp_set_secondary_soft_back_light(void __iomem *regs,
+					bool soft_on)
+{
+	/* 3X5.D3[1] - FP Secondary Software Back Light On
+	 *             0: Off
+	 *             1: On */
+	svga_wcrt_mask(regs, 0xD3,
+			soft_on ? BIT(1) : 0x00, BIT(1));
+	DRM_DEBUG_KMS("FP Secondary Software Controlled Back Light: "
+			"%s\n", soft_on ? "On" : "Off");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit 83e048f7a0e05fd6877732c8561baee9eeefacbb
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 22:43:43 2017 -0500

    Added via_fp_set_secondary_power_seq_type
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index cb2fae3eea7..0e7850e317e 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -436,6 +436,24 @@ via_fp_set_primary_hard_power(void __iomem *regs, bool power_state)
 }
 
 /*
+ * Sets CX700 / VX700 or later chipset's FP secondary
+ * power sequence control type.
+ */
+static inline void
+via_fp_set_secondary_power_seq_type(void __iomem *regs,
+					bool ctrl_type)
+{
+	/* 3X5.D3[0] - FP Secondary Power Sequence Control Type
+	 *             0: Hardware Control
+	 *             1: Software Control */
+	svga_wcrt_mask(regs, 0xD3,
+			ctrl_type ? 0x00 : BIT(0), BIT(0));
+	DRM_DEBUG_KMS("FP Secondary Power Sequence Control Type: "
+			"%s Control\n",
+			ctrl_type ? "Hardware" : "Software");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit 9790653fb663878c7d0d86aab24a3a5ee0444f3a
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 22:12:35 2017 -0500

    Added via_fp_set_primary_hard_power
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index 8786840fdf4..cb2fae3eea7 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -420,6 +420,22 @@ via_fp_set_primary_direct_display_period(void __iomem *regs, bool direct_on)
 }
 
 /*
+ * Sets KM400 or later chipset's FP primary hardware controlled
+ * power sequence.
+ */
+static inline void
+via_fp_set_primary_hard_power(void __iomem *regs, bool power_state)
+{
+	/* 3X5.6A[3] - FP Primary Hardware Controlled Power Sequence
+	 *             0: Hardware Controlled Power Off
+	 *             1: Hardware Controlled Power On */
+	svga_wcrt_mask(regs, 0x6A,
+			power_state ? BIT(3) : 0x00, BIT(3));
+	DRM_DEBUG_KMS("FP Primary Hardware Controlled Power "
+			"Sequence: %s\n", power_state ? "On" : "Off");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit 69888e5b0301de2234f38d5266233e85a3e1e0bc
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 22:02:57 2017 -0500

    Added via_fp_set_primary_direct_display_period
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index 4c8378cdffc..8786840fdf4 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -404,6 +404,22 @@ via_fp_set_primary_direct_back_light_ctrl(void __iomem *regs, bool direct_on)
 }
 
 /*
+ * Sets KM400 or later chipset's FP primary direct display
+ * period control.
+ */
+static inline void
+via_fp_set_primary_direct_display_period(void __iomem *regs, bool direct_on)
+{
+	/* 3X5.91[7] - FP Primary Direct Display Period Control
+	 *             0: On
+	 *             1: Off */
+	svga_wcrt_mask(regs, 0x91,
+			direct_on ? 0x00 : BIT(7), BIT(7));
+	DRM_DEBUG_KMS("FP Primary Direct Display Period Control: %s\n",
+			direct_on ? "On" : "Off");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit 19847441af97646d7164b5cd6713bf646d231bba
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 21:55:42 2017 -0500

    Added via_fp_set_primary_direct_back_light_ctrl
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index cbe1e4a1e15..4c8378cdffc 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -388,6 +388,22 @@ via_fp_set_primary_soft_vdd(void __iomem *regs, bool soft_on)
 }
 
 /*
+ * Sets KM400 or later chipset's FP primary direct back
+ * light control.
+ */
+static inline void
+via_fp_set_primary_direct_back_light_ctrl(void __iomem *regs, bool direct_on)
+{
+	/* 3X5.91[6] - FP Primary Direct Back Light Control
+	 *             0: On
+	 *             1: Off */
+	svga_wcrt_mask(regs, 0x91,
+			direct_on ? 0x00 : BIT(6), BIT(6));
+	DRM_DEBUG_KMS("FP Primary Direct Back Light Control: %s\n",
+			direct_on ? "On" : "Off");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit ea48c56bf98880cf1f9d4fffbcd64c9f6d08bf4e
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 21:48:47 2017 -0500

    Added via_fp_set_primary_soft_vdd
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index 9ed671eda01..cbe1e4a1e15 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -372,6 +372,22 @@ via_fp_set_primary_soft_data(void __iomem *regs, bool soft_on)
 }
 
 /*
+ * Sets KM400 or later chipset's FP primary software controlled
+ * VDD.
+ */
+static inline void
+via_fp_set_primary_soft_vdd(void __iomem *regs, bool soft_on)
+{
+	/* 3X5.91[4] - FP Primary Software VDD On
+	 *             0: Off
+	 *             1: On */
+	svga_wcrt_mask(regs, 0x91,
+			soft_on ? BIT(4) : 0x00, BIT(4));
+	DRM_DEBUG_KMS("FP Primary Software Controlled VDD: %s\n",
+			soft_on ? "On" : "Off");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit 1aef2630bb7e0723310cefd56f9e368bb50036f8
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 21:41:51 2017 -0500

    Added via_fp_set_primary_soft_data
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index 5e2b692777f..9ed671eda01 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -356,6 +356,22 @@ via_fp_set_primary_soft_vee(void __iomem *regs, bool soft_on)
 }
 
 /*
+ * Sets KM400 or later chipset's FP primary software controlled
+ * data.
+ */
+static inline void
+via_fp_set_primary_soft_data(void __iomem *regs, bool soft_on)
+{
+	/* 3X5.91[3] - FP Primary Software Data On
+	 *             0: Off
+	 *             1: On */
+	svga_wcrt_mask(regs, 0x91,
+			soft_on ? BIT(3) : 0x00, BIT(3));
+	DRM_DEBUG_KMS("FP Primary Software Controlled Data: %s\n",
+			soft_on ? "On" : "Off");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit 4720cdacf588aa5e6d4691a9a83efd66e85e16a6
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 20:57:52 2017 -0500

    Added via_fp_set_primary_soft_vee
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index 35b378be6cc..5e2b692777f 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -340,6 +340,22 @@ via_fp_set_primary_soft_back_light(void __iomem *regs, bool soft_on)
 }
 
 /*
+ * Sets KM400 or later chipset's FP primary software controlled
+ * VEE.
+ */
+static inline void
+via_fp_set_primary_soft_vee(void __iomem *regs, bool soft_on)
+{
+	/* 3X5.91[2] - FP Primary Software VEE On
+	 *             0: Off
+	 *             1: On */
+	svga_wcrt_mask(regs, 0x91,
+			soft_on ? BIT(2) : 0x00, BIT(2));
+	DRM_DEBUG_KMS("FP Primary Software Controlled VEE: %s\n",
+			soft_on ? "On" : "Off");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit 77676ec7e0cfc0cef088f401ae0873babeb9d177
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 20:51:58 2017 -0500

    Added via_fp_set_primary_soft_back_light
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index e4e780fed3e..35b378be6cc 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -324,6 +324,22 @@ via_fp_set_primary_power_seq_type(void __iomem *regs, bool ctrl_type)
 }
 
 /*
+ * Sets KM400 or later chipset's FP primary software controlled
+ * back light.
+ */
+static inline void
+via_fp_set_primary_soft_back_light(void __iomem *regs, bool soft_on)
+{
+	/* 3X5.91[1] - FP Primary Software Back Light On
+	 *             0: Off
+	 *             1: On */
+	svga_wcrt_mask(regs, 0x91,
+			soft_on ? BIT(1) : 0x00, BIT(1));
+	DRM_DEBUG_KMS("FP Primary Software Controlled Back Light: "
+			"%s\n", soft_on ? "On" : "Off");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit de23a40d47a06c2f7eb8ea6c02e2417c03fab668
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 20:43:11 2017 -0500

    Added via_fp_set_primary_power_seq_type
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index b7394a9df46..e4e780fed3e 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -307,6 +307,23 @@ via_analog_set_display_source(void __iomem *regs, u8 display_source)
 }
 
 /*
+ * Sets KM400 or later chipset's FP primary power sequence control
+ * type.
+ */
+static inline void
+via_fp_set_primary_power_seq_type(void __iomem *regs, bool ctrl_type)
+{
+	/* 3X5.91[0] - FP Primary Power Sequence Control Type
+	 *             0: Hardware Control
+	 *             1: Software Control */
+	svga_wcrt_mask(regs, 0x91,
+			ctrl_type ? 0x00 : BIT(0), BIT(0));
+	DRM_DEBUG_KMS("FP Primary Power Sequence Control Type: "
+			"%s Control\n",
+			ctrl_type ? "Hardware" : "Software");
+}
+
+/*
  * Sets FPDP (Flat Panel Display Port) Low I/O pad state.
  */
 static inline void
commit 5696b4ae31a68b6260fb9ed4e08558dcc11f6f5b
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 20:23:56 2017 -0500

    Correcting a serious mistake inside via_fpdp_high_set_io_pad_state
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index e81839ce7d0..b7394a9df46 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -355,7 +355,7 @@ via_fpdp_high_set_io_pad_state(void __iomem *regs, u8 io_pad_state)
 	 *               10: Depend on the other control signal
 	 *               11: Pad on/off according to the
 	 *                   Power Management Status (PMS) */
-	svga_wcrt_mask(regs, 0x2A,
+	svga_wseq_mask(regs, 0x2A,
 			io_pad_state << 2, BIT(3) | BIT(2));
 	DRM_DEBUG_KMS("FPDP High I/O Pad State: %s\n",
 			((io_pad_state & (BIT(1) | BIT(0))) == 0x03) ?
commit 4a985ab935f851e141c03eac43326fc80ddd0b15
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Thu Jul 6 20:19:43 2017 -0500

    Correcting a serious mistake inside via_fpdp_low_set_io_pad_state
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index 752c46d9ab2..e81839ce7d0 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -317,7 +317,7 @@ via_fpdp_low_set_io_pad_state(void __iomem *regs, u8 io_pad_state)
 	 *               10: Depend on the other control signal
 	 *               11: Pad on/off according to the
 	 *                   Power Management Status (PMS) */
-	svga_wcrt_mask(regs, 0x2A,
+	svga_wseq_mask(regs, 0x2A,
 			io_pad_state, BIT(1) | BIT(0));
 	DRM_DEBUG_KMS("FPDP Low I/O Pad State: %s\n",
 			((io_pad_state & (BIT(1) | BIT(0))) == 0x03) ?
commit c95977faf4cfbe836834ffb4649154f884d7d69b
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Tue Jul 4 14:43:52 2017 -0500

    Stylistic clean up of inline functions inside crtc_hw.h
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index e649d5061e5..752c46d9ab2 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -234,72 +234,76 @@ via_dvp1_set_display_source(void __iomem *regs, u8 display_source)
 }
 
 /*
- * Sets analog (VGA) DAC output state.
+ * Sets analog (VGA) DAC power.
  */
 static inline void
-via_analog_set_power(void __iomem *regs, bool outputState)
+via_analog_set_power(void __iomem *regs, bool output_state)
 {
 	/* 3X5.47[2] - DACOFF Backdoor Register
 	 *             0: DAC on
 	 *             1: DAC off */
-	svga_wcrt_mask(regs, 0x47, outputState ? 0x00 : BIT(2),
-			BIT(2));
+	svga_wcrt_mask(regs, 0x47,
+			output_state ? 0x00 : BIT(2), BIT(2));
 	DRM_DEBUG_KMS("Analog (VGA) Power: %s\n",
-			outputState ? "On" : "Off");
+			output_state ? "On" : "Off");
 }
 
 /*
  * Sets analog (VGA) DPMS state.
  */
 static inline void
-via_analog_set_dpms_control(void __iomem *regs, u8 dpmsControl)
+via_analog_set_dpms_control(void __iomem *regs, u8 dpms_control)
 {
 	/* 3X5.36[5:4] - DPMS Control
 	 *               00: On
 	 *               01: Stand-by
 	 *               10: Suspend
 	 *               11: Off */
-	svga_wcrt_mask(regs, 0x36, dpmsControl << 4, BIT(5) | BIT(4));
+	svga_wcrt_mask(regs, 0x36,
+			dpms_control << 4, BIT(5) | BIT(4));
 	DRM_DEBUG_KMS("Analog (VGA) DPMS: %s\n",
-			((dpmsControl & (BIT(1) | BIT(0))) == 0x03) ? "Off" :
-			((dpmsControl & (BIT(1) | BIT(0))) == 0x02) ? "Suspend" :
-			((dpmsControl & (BIT(1) | BIT(0))) == 0x01) ? "Standby" :
-								      "On");
+			((dpms_control & (BIT(1) | BIT(0))) == 0x03) ?
+				"Off" :
+			((dpms_control & (BIT(1) | BIT(0))) == 0x02) ?
+				"Suspend" :
+			((dpms_control & (BIT(1) | BIT(0))) == 0x01) ?
+				"Standby" :
+				"On");
 }
 
 /*
  * Sets analog (VGA) sync polarity.
  */
 static inline void
-via_analog_set_sync_polarity(void __iomem *regs, u8 syncPolarity)
+via_analog_set_sync_polarity(void __iomem *regs, u8 sync_polarity)
 {
-	/* Set analog (VGA) sync polarity. */
 	/* 3C2[7] - Analog Vertical Sync Polarity
 	 *          0: Positive
 	 *          1: Negative
 	 * 3C2[6] - Analog Horizontal Sync Polarity
 	 *          0: Positive
 	 *          1: Negative */
-	svga_wmisc_mask(regs, syncPolarity << 6, (BIT(1) | BIT(0)) << 6);
+	svga_wmisc_mask(regs,
+			sync_polarity << 6, (BIT(1) | BIT(0)) << 6);
 	DRM_DEBUG_KMS("Analog (VGA) Horizontal Sync Polarity: %s\n",
-			(syncPolarity & BIT(0)) ? "-" : "+");
+			(sync_polarity & BIT(0)) ? "-" : "+");
 	DRM_DEBUG_KMS("Analog (VGA) Vertical Sync Polarity: %s\n",
-			(syncPolarity & BIT(1)) ? "-" : "+");
+			(sync_polarity & BIT(1)) ? "-" : "+");
 }
 
 /*
  * Sets analog (VGA) display source.
  */
 static inline void
-via_analog_set_display_source(void __iomem *regs, u8 displaySource)
+via_analog_set_display_source(void __iomem *regs, u8 display_source)
 {
-	/* Set analog (VGA) display source. */
 	/* 3C5.16[6] - CRT Display Source
 	 *             0: Primary Display Stream (IGA1)
 	 *             1: Secondary Display Stream (IGA2) */
-	svga_wseq_mask(regs, 0x16, displaySource << 6, BIT(6));
+	svga_wseq_mask(regs, 0x16,
+			display_source << 6, BIT(6));
 	DRM_DEBUG_KMS("Analog (VGA) Display Source: IGA%d\n",
-			(displaySource & 0x01) + 1);
+			(display_source & 0x01) + 1);
 }
 
 /*
@@ -313,12 +317,16 @@ via_fpdp_low_set_io_pad_state(void __iomem *regs, u8 io_pad_state)
 	 *               10: Depend on the other control signal
 	 *               11: Pad on/off according to the
 	 *                   Power Management Status (PMS) */
-	svga_wcrt_mask(regs, 0x2A, io_pad_state, BIT(1) | BIT(0));
+	svga_wcrt_mask(regs, 0x2A,
+			io_pad_state, BIT(1) | BIT(0));
 	DRM_DEBUG_KMS("FPDP Low I/O Pad State: %s\n",
-			((io_pad_state & (BIT(1) | BIT(0))) == 0x03) ? "On" :
-			((io_pad_state & (BIT(1) | BIT(0))) == 0x02) ? "Conditional" :
-			((io_pad_state & (BIT(1) | BIT(0))) == 0x01) ? "Off" :
-								       "Off");
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x03) ?
+				"On" :
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x02) ?
+				"Conditional" :
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x01) ?
+				"Off" :
+				"Off");
 }
 
 /*
@@ -330,13 +338,14 @@ via_fpdp_low_set_display_source(void __iomem *regs, u8 display_source)
 	/* 3X5.99[4] - FPDP Low Data Source Selection
 	 *             0: Primary Display
 	 *             1: Secondary Display */
-	svga_wcrt_mask(regs, 0x99, display_source << 4, BIT(4));
+	svga_wcrt_mask(regs, 0x99,
+			display_source << 4, BIT(4));
 	DRM_DEBUG_KMS("FPDP Low Display Source: IGA%d\n",
 			(display_source & 0x01) + 1);
 }
 
 /*
- * Sets FPDP (Flat Panel Display Port) High I/O pad state
+ * Sets FPDP (Flat Panel Display Port) High I/O pad state.
  */
 static inline void
 via_fpdp_high_set_io_pad_state(void __iomem *regs, u8 io_pad_state)
@@ -346,12 +355,16 @@ via_fpdp_high_set_io_pad_state(void __iomem *regs, u8 io_pad_state)
 	 *               10: Depend on the other control signal
 	 *               11: Pad on/off according to the
 	 *                   Power Management Status (PMS) */
-	svga_wcrt_mask(regs, 0x2A, io_pad_state << 2, BIT(3) | BIT(2));
+	svga_wcrt_mask(regs, 0x2A,
+			io_pad_state << 2, BIT(3) | BIT(2));
 	DRM_DEBUG_KMS("FPDP High I/O Pad State: %s\n",
-			((io_pad_state & (BIT(1) | BIT(0))) == 0x03) ? "On" :
-			((io_pad_state & (BIT(1) | BIT(0))) == 0x02) ? "Conditional" :
-			((io_pad_state & (BIT(1) | BIT(0))) == 0x01) ? "Off" :
-								       "Off");
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x03) ?
+				"On" :
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x02) ?
+				"Conditional" :
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x01) ?
+				"Off" :
+				"Off");
 }
 
 /*
@@ -363,7 +376,8 @@ via_fpdp_high_set_display_source(void __iomem *regs, u8 display_source)
 	/* 3X5.97[4] - FPDP High Data Source Selection
 	 *             0: Primary Display
 	 *             1: Secondary Display */
-	svga_wcrt_mask(regs, 0x97, display_source << 4, BIT(4));
+	svga_wcrt_mask(regs, 0x97,
+			display_source << 4, BIT(4));
 	DRM_DEBUG_KMS("FPDP High Display Source: IGA%d\n",
 			(display_source & 0x01) + 1);
 }
@@ -442,16 +456,20 @@ via_lvds1_set_io_pad_setting(void __iomem *regs, u8 io_pad_state)
 	 *               10: Depend on the other control signal
 	 *               11: Pad on/off according to the
 	 *                   Power Management Status (PMS) */
-	svga_wcrt_mask(regs, 0x2A, io_pad_state, BIT(1) | BIT(0));
+	svga_wcrt_mask(regs, 0x2A,
+			io_pad_state, BIT(1) | BIT(0));
 	DRM_DEBUG_KMS("LVDS1 I/O Pad State: %s\n",
-			((io_pad_state & (BIT(1) | BIT(0))) == 0x03) ? "On" :
-			((io_pad_state & (BIT(1) | BIT(0))) == 0x02) ? "Conditional" :
-			((io_pad_state & (BIT(1) | BIT(0))) == 0x01) ? "Off" :
-								       "Off");
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x03) ?
+				"On" :
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x02) ?
+				"Conditional" :
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x01) ?
+				"Off" :
+				"Off");
 }
 
 /*
- * Sets CX700 or later single chipset's LVDS1 display source.
+ * Sets LVDS1 display source.
  */
 static inline void
 via_lvds1_set_display_source(void __iomem *regs, u8 display_source)
@@ -459,7 +477,8 @@ via_lvds1_set_display_source(void __iomem *regs, u8 display_source)
 	/* 3X5.99[4] - LVDS Channel 1 Data Source Selection
 	 *             0: Primary Display
 	 *             1: Secondary Display */
-	svga_wcrt_mask(regs, 0x99, display_source << 4, BIT(4));
+	svga_wcrt_mask(regs, 0x99,
+			display_source << 4, BIT(4));
 	DRM_DEBUG_KMS("LVDS1 Display Source: IGA%d\n",
 			(display_source & 0x01) + 1);
 }
@@ -475,16 +494,20 @@ via_lvds2_set_io_pad_setting(void __iomem *regs, u8 io_pad_state)
 	 *               10: Depend on the other control signal
 	 *               11: Pad on/off according to the
 	 *                   Power Management Status (PMS) */
-	svga_wcrt_mask(regs, 0x2A, io_pad_state << 2, BIT(3) | BIT(2));
+	svga_wcrt_mask(regs, 0x2A,
+			io_pad_state << 2, BIT(3) | BIT(2));
 	DRM_DEBUG_KMS("LVDS2 I/O Pad State: %s\n",
-			((io_pad_state & (BIT(1) | BIT(0))) == 0x03) ? "On" :
-			((io_pad_state & (BIT(1) | BIT(0))) == 0x02) ? "Conditional" :
-			((io_pad_state & (BIT(1) | BIT(0))) == 0x01) ? "Off" :
-								       "Off");
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x03) ?
+				"On" :
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x02) ?
+				"Conditional" :
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x01) ?
+				"Off" :
+				"Off");
 }
 
 /*
- * Sets CX700 or later single chipset's LVDS2 display source.
+ * Sets LVDS2 display source.
  */
 static inline void
 via_lvds2_set_display_source(void __iomem *regs, u8 display_source)
@@ -492,7 +515,8 @@ via_lvds2_set_display_source(void __iomem *regs, u8 display_source)
 	/* 3X5.97[4] - LVDS Channel 2 Data Source Selection
 	 *             0: Primary Display
 	 *             1: Secondary Display */
-	svga_wcrt_mask(regs, 0x97, display_source << 4, BIT(4));
+	svga_wcrt_mask(regs, 0x97,
+			display_source << 4, BIT(4));
 	DRM_DEBUG_KMS("LVDS2 Display Source: IGA%d\n",
 			(display_source & 0x01) + 1);
 }
@@ -503,11 +527,11 @@ via_lvds2_set_display_source(void __iomem *regs, u8 display_source)
 static inline void
 via_tmds_set_power(void __iomem *regs, bool powerState)
 {
-	/* Set TMDS (DVI) power state. */
 	/* 3X5.D2[3] - Power Down (Active High) for DVI
 	 *             0: TMDS power on
 	 *             1: TMDS power down */
-	svga_wcrt_mask(regs, 0xD2, powerState ? 0 : BIT(3), BIT(3));
+	svga_wcrt_mask(regs, 0xD2,
+			powerState ? 0x00 : BIT(3), BIT(3));
 	DRM_DEBUG_KMS("TMDS (DVI) Power State: %s\n",
 			powerState ? "On" : "Off");
 }
@@ -525,7 +549,8 @@ via_tmds_set_sync_polarity(void __iomem *regs, u8 syncPolarity)
 	 * 3X5.97[5] - DVI (TMDS) HSYNC Polarity
 	 *              0: Positive
 	 *              1: Negative */
-	svga_wcrt_mask(regs, 0x97, syncPolarity << 5, BIT(6) | BIT(5));
+	svga_wcrt_mask(regs, 0x97,
+			syncPolarity << 5, BIT(6) | BIT(5));
 	DRM_DEBUG_KMS("TMDS (DVI) Horizontal Sync Polarity: %s\n",
 			(syncPolarity & BIT(0)) ? "-" : "+");
 	DRM_DEBUG_KMS("TMDS (DVI) Vertical Sync Polarity: %s\n",
@@ -538,13 +563,13 @@ via_tmds_set_sync_polarity(void __iomem *regs, u8 syncPolarity)
 static inline void
 via_tmds_set_display_source(void __iomem *regs, u8 displaySource)
 {
-	/* Set TMDS (DVI) display source.
-	 * The integrated TMDS transmitter appears to utilize LVDS1's
+	/* The integrated TMDS transmitter appears to utilize LVDS1's
 	 * data source selection bit (3X5.99[4]). */
 	/* 3X5.99[4] - LVDS Channel1 Data Source Selection
 	 *             0: Primary Display
 	 *             1: Secondary Display */
-	svga_wcrt_mask(regs, 0x99, displaySource << 4, BIT(4));
+	svga_wcrt_mask(regs, 0x99,
+			displaySource << 4, BIT(4));
 	DRM_DEBUG_KMS("TMDS (DVI) Display Source: IGA%d\n",
 			(displaySource & 0x01) + 1);
 }
commit e55ba9e19483aade454436338c2f9d63e8a338ea
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Tue Jul 4 13:47:36 2017 -0500

    Added via_dvp1_set_data_drive_strength
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index bd8fbd28907..e649d5061e5 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -202,6 +202,24 @@ via_dvp1_set_clock_drive_strength(void __iomem *regs,
 }
 
 /*
+ * Sets DVP1 (Digital Video Port 1) data I/O pads drive strength.
+ */
+static inline void
+via_dvp1_set_data_drive_strength(void __iomem *regs,
+					u8 data_drive_strength)
+{
+	/* 3C5.65[1:0] - DVP1 Data Pads Driving Select [1:0}
+	 *               00: lowest
+	 *               01: low
+	 *               10: high
+	 *               11: highest */
+	svga_wseq_mask(regs, 0x65,
+			data_drive_strength, BIT(1) | BIT(0));
+	DRM_DEBUG_KMS("DVP1 Data I/O Pads Drive Strength: %lu\n",
+			data_drive_strength & (BIT(1) | BIT(0)));
+}
+
+/*
  * Sets the display source of DVP1 (Digital Video Port 1) interface.
  */
 static inline void
commit b6b5325157aab6cb173762435dd49059230698e4
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Tue Jul 4 13:29:12 2017 -0500

    Added via_dvp1_set_clock_drive_strength
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index af17c05c3ec..bd8fbd28907 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -184,6 +184,24 @@ via_dvp1_set_io_pad_state(void __iomem *regs, u8 io_pad_state)
 }
 
 /*
+ * Sets DVP1 (Digital Video Port 1) clock I/O pad drive strength.
+ */
+static inline void
+via_dvp1_set_clock_drive_strength(void __iomem *regs,
+					u8 clock_drive_strength)
+{
+	/* 3C5.65[3:2] - DVP1 Clock Pads Driving Select [1:0]
+	 *               00: lowest
+	 *               01: low
+	 *               10: high
+	 *               11: highest */
+	svga_wseq_mask(regs, 0x65,
+			clock_drive_strength << 2, BIT(3) | BIT(2));
+	DRM_DEBUG_KMS("DVP1 Clock I/O Pad Drive Strength: %lu\n",
+			clock_drive_strength & (BIT(1) | BIT(0)));
+}
+
+/*
  * Sets the display source of DVP1 (Digital Video Port 1) interface.
  */
 static inline void
commit b7281b509bf267049951992bfeffc0f6541ba5a1
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Tue Jul 4 13:16:02 2017 -0500

    Added via_dvp0_set_data_drive_strength
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index f9a7588f57a..af17c05c3ec 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -132,6 +132,25 @@ via_dvp0_set_clock_drive_strength(void __iomem *regs,
 }
 
 /*
+ * Sets DVP0 (Digital Video Port 0) data I/O pads drive strength.
+ */
+static inline void
+via_dvp0_set_data_drive_strength(void __iomem *regs,
+					u8 data_drive_strength)
+{
+	/* 3C5.1B[1] - DVP0 Data Drive Strength Bit [0] */
+	svga_wseq_mask(regs, 0x1B,
+			data_drive_strength << 1, BIT(1));
+
+	/* 3C5.2A[5] - DVP0 Data Drive Strength Bit [1] */
+	svga_wseq_mask(regs, 0x2A,
+			data_drive_strength << 4, BIT(5));
+
+	DRM_DEBUG_KMS("DVP0 Data I/O Pads Drive Strength: %lu\n",
+			data_drive_strength & (BIT(1) | BIT(0)));
+}
+
+/*
  * Sets the display source of DVP0 (Digital Video Port 0) interface.
  */
 static inline void
commit 5331a19fda4ee75ff3699d53921d85d3bc950ba7
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Tue Jul 4 13:06:12 2017 -0500

    Added via_dvp0_set_clock_drive_strength
    
    This is an inline function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/crtc_hw.h b/drivers/gpu/drm/via/crtc_hw.h
index 9885f5ce523..f9a7588f57a 100644
--- a/drivers/gpu/drm/via/crtc_hw.h
+++ b/drivers/gpu/drm/via/crtc_hw.h
@@ -113,6 +113,25 @@ via_dvp0_set_io_pad_state(void __iomem *regs, u8 io_pad_state)
 }
 
 /*
+ * Sets DVP0 (Digital Video Port 0) clock I/O pad drive strength.
+ */
+static inline void
+via_dvp0_set_clock_drive_strength(void __iomem *regs,
+					u8 clock_drive_strength)
+{
+	/* 3C5.1E[2] - DVP0 Clock Drive Strength Bit [0] */
+	svga_wseq_mask(regs, 0x1E,
+			clock_drive_strength << 2, BIT(2));
+
+	/* 3C5.2A[4] - DVP0 Clock Drive Strength Bit [1] */
+	svga_wseq_mask(regs, 0x2A,
+			clock_drive_strength << 3, BIT(4));
+
+	DRM_DEBUG_KMS("DVP0 Clock I/O Pad Drive Strength: %lu\n",
+			clock_drive_strength & (BIT(1) | BIT(0)));
+}
+
+/*
  * Sets the display source of DVP0 (Digital Video Port 0) interface.
  */
 static inline void
commit d1d0f475b1e1326df299bdd162e782b9378ecfff
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Tue Jul 4 03:11:53 2017 -0500

    Version bumped to 3.0.38
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/via_drv.h b/drivers/gpu/drm/via/via_drv.h
index 6704b382f80..079f4405c8d 100644
--- a/drivers/gpu/drm/via/via_drv.h
+++ b/drivers/gpu/drm/via/via_drv.h
@@ -34,7 +34,7 @@
 
 #define DRIVER_MAJOR		3
 #define DRIVER_MINOR		0
-#define DRIVER_PATCHLEVEL	37
+#define DRIVER_PATCHLEVEL	38
 
 #include <linux/module.h>
 
commit 6fe68452579d63ca08d4d6dbced230e9a95a91ad
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Tue Jul 4 03:00:53 2017 -0500

    Added via_fp_mode_set
    
    As an interim solution, the code from via_set_sync_polarity callback
    function was imported with modifications made to via_fp_mode_set
    callback function.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/via_fp.c b/drivers/gpu/drm/via/via_fp.c
index a60a82b66aa..238f3b6c9ba 100644
--- a/drivers/gpu/drm/via/via_fp.c
+++ b/drivers/gpu/drm/via/via_fp.c
@@ -433,10 +433,60 @@ via_lvds_mode_fixup(struct drm_encoder *encoder,
 	return true;
 }
 
+static void
+via_fp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
+		struct drm_display_mode *adjusted_mode)
+{
+	struct via_crtc *iga = container_of(encoder->crtc, struct via_crtc, base);
+	struct via_encoder *enc = container_of(encoder, struct via_encoder, base);
+	struct via_device *dev_priv = encoder->dev->dev_private;
+	u8 syncreg = 0;
+
+	DRM_DEBUG_KMS("Entered via_fp_mode_set.\n");
+
+	if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
+		syncreg |= BIT(6);
+	if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
+		syncreg |= BIT(5);
+
+	switch (enc->di_port) {
+	case VIA_DI_PORT_DVP0:
+		svga_wcrt_mask(VGABASE, 0x96, syncreg, BIT(6) | BIT(5));
+		break;
+
+	case VIA_DI_PORT_DVP1:
+		svga_wcrt_mask(VGABASE, 0x9B, syncreg, BIT(6) | BIT(5));
+		break;
+
+	case VIA_DI_PORT_DFPH:
+		svga_wcrt_mask(VGABASE, 0x97, syncreg, BIT(6) | BIT(5));
+		break;
+
+	case VIA_DI_PORT_DFPL:
+		svga_wcrt_mask(VGABASE, 0x99, syncreg, BIT(6) | BIT(5));
+		break;
+
+	/* For TTL Type LCD */
+	case (VIA_DI_PORT_DFPL + VIA_DI_PORT_DVP1):
+		svga_wcrt_mask(VGABASE, 0x99, syncreg, BIT(6) | BIT(5));
+		svga_wcrt_mask(VGABASE, 0x9B, syncreg, BIT(6) | BIT(5));
+		break;
+
+	default:
+		DRM_ERROR("No DIPort.\n");
+	case VIA_DI_PORT_NONE:
+		break;
+	}
+
+	via_fp_display_source(dev_priv, enc->di_port, iga->index);
+
+	DRM_DEBUG_KMS("Exiting via_fp_mode_set.\n");
+}
+
 const struct drm_encoder_helper_funcs via_lvds_helper_funcs = {
 	.dpms = via_fp_dpms,
 	.mode_fixup = via_lvds_mode_fixup,
-	.mode_set = via_set_sync_polarity,
+	.mode_set = via_fp_mode_set,
 	.prepare = via_encoder_prepare,
 	.commit = via_encoder_commit,
 	.disable = via_encoder_disable,
commit dc4f06c03fdf38a5d8734f028ac5dfab2bdc8260
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Tue Jul 4 02:57:21 2017 -0500

    Trimming unnecessary code from via_fp_dpms
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/via/via_fp.c b/drivers/gpu/drm/via/via_fp.c
index b7e90b8ac0d..a60a82b66aa 100644
--- a/drivers/gpu/drm/via/via_fp.c
+++ b/drivers/gpu/drm/via/via_fp.c
@@ -331,13 +331,11 @@ via_fp_dpms(struct drm_encoder *encoder, int mode)
 	struct via_encoder *enc = container_of(encoder, struct via_encoder, base);
 	struct via_device *dev_priv = encoder->dev->dev_private;
 	struct drm_device *dev = encoder->dev;
-	struct via_crtc *iga = NULL;
 
 	switch (mode) {
 	case DRM_MODE_DPMS_ON:
 		if (encoder->crtc == NULL)
 			return;
-		iga = container_of(encoder->crtc, struct via_crtc, base);
 
 		/* when using the EPIA-EX board, if we do not set this bit,
 		 * light LCD will failed in nonRandR structure,


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