[Openchrome-devel] drm-openchrome: Branch 'drm-next-4.16' - 4 commits - drivers/gpu/drm

[Kevin Brace]

 drivers/gpu/drm/openchrome/via_crtc.c     |   20 ++++++++++----------
 drivers/gpu/drm/openchrome/via_disp_reg.h |    4 ++--
 drivers/gpu/drm/openchrome/via_drv.h      |    2 +-
 3 files changed, 13 insertions(+), 13 deletions(-)

New commits:
commit 86dad52a7eaaa933626fce8afe718b52c9104fe3
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Sat Feb 3 15:13:51 2018 -0800

    drm/openchrome: Version bumped to 3.0.71
    
    An important CLE266 chipset display regression fix got implemented.
    The correct functionality was validated on VIA EPIA-M mainboard.
    Standby resume (ACPI S3 State resume) is also working for EPIA-M now.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/openchrome/via_drv.h b/drivers/gpu/drm/openchrome/via_drv.h
index de4beb522b9d..39e0eb4d40d0 100644
--- a/drivers/gpu/drm/openchrome/via_drv.h
+++ b/drivers/gpu/drm/openchrome/via_drv.h
@@ -34,7 +34,7 @@
 
 #define DRIVER_MAJOR		3
 #define DRIVER_MINOR		0
-#define DRIVER_PATCHLEVEL	70
+#define DRIVER_PATCHLEVEL	71
 
 #include <linux/module.h>
 
commit 629042904c2e04b1b8178f6f968fe8580ff65ada
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Sat Feb 3 15:08:02 2018 -0800

    drm/openchrome: Cosmetic changes to display FIFO depth formula
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/openchrome/via_disp_reg.h b/drivers/gpu/drm/openchrome/via_disp_reg.h
index a3b2cf8ddcbe..e2bd895bb495 100644
--- a/drivers/gpu/drm/openchrome/via_disp_reg.h
+++ b/drivers/gpu/drm/openchrome/via_disp_reg.h
@@ -28,8 +28,8 @@
 /********************************************************/
 /* Definition IGA Design Method of FIFO Registers	*/
 /********************************************************/
-#define IGA1_FIFO_DEPTH_SELECT_FORMULA(x)		((x / 2) - 1)
-#define IGA2_FIFO_DEPTH_SELECT_FORMULA(x)		((x / 2) / 4) - 1
+#define IGA1_FIFO_DEPTH_SELECT_FORMULA(x)		((x >> 1) - 1)
+#define IGA2_FIFO_DEPTH_SELECT_FORMULA(x)		((x >> 3) - 1)
 
 /* Define Display OFFSET */
 /* VT3314 chipset */
commit ee55444ee94a21b019c2e6610f4e5e3b3ddab9db
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Sat Feb 3 15:06:43 2018 -0800

    drm/openchrome: KM400 IGA1 display FIFO parameter comment fix
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/openchrome/via_crtc.c b/drivers/gpu/drm/openchrome/via_crtc.c
index 82101bce2c94..dde69f84d503 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -629,22 +629,22 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
 	case PCI_DEVICE_ID_VIA_KM400:
 		if ((mode->hdisplay >= 1600) &&
 			(dev_priv->vram_type <= VIA_MEM_DDR_200)) {
-			/* SR17[7:0] */
+			/* SR17[6:0] */
 			fifo_max_depth = 58;
 
-			/* SR16[7], SR16[5:0] */
+			/* SR16[5:0] */
 			fifo_threshold = 24;
 
-			/* SR18[7], SR18[5:0] */
+			/* SR18[5:0] */
 			fifo_high_threshold = 92;
 		} else {
-			/* SR17[7:0] */
+			/* SR17[6:0] */
 			fifo_max_depth = 128;
 
-			/* SR16[7], SR16[5:0] */
+			/* SR16[5:0] */
 			fifo_threshold = 112;
 
-			/* SR18[7], SR18[5:0] */
+			/* SR18[5:0] */
 			fifo_high_threshold = 92;
 		}
 
commit 398271737eb38c05be47d551d1976b85d202b083
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Sat Feb 3 15:05:42 2018 -0800

    drm/openchrome: Fix for CLE266 IGA1 display regression
    
    The new CLE266 chipset IGA1 display FIFO parameters were severely
    disrupting IGA1 display. This commit fixes this bug. Also, with this
    fix, mode setting of IGA1 with analog (VGA) output after standby
    resumeis now fully working. This fix was validated on VIA EPIA-M
    mainboard.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/openchrome/via_crtc.c b/drivers/gpu/drm/openchrome/via_crtc.c
index e0f14a8499e7..82101bce2c94 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -509,7 +509,7 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
 		if (dev_priv->revision == CLE266_REVISION_AX) {
 			if (mode->hdisplay > 1024) {
 				/* SR17[6:0] */
-				fifo_max_depth = 192;
+				fifo_max_depth = 96;
 
 				/* SR16[5:0] */
 				fifo_threshold = 92;
@@ -520,7 +520,7 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
 				enable_extended_display_fifo = true;
 			} else {
 				/* SR17[6:0] */
-				fifo_max_depth = 128;
+				fifo_max_depth = 64;
 
 				/* SR16[5:0] */
 				fifo_threshold = 32;
@@ -576,7 +576,7 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
 		} else {
 			if (mode->hdisplay >= 1024) {
 				/* SR17[6:0] */
-				fifo_max_depth = 256;
+				fifo_max_depth = 128;
 
 				/* SR16[5:0] */
 				fifo_threshold = 112;
@@ -587,7 +587,7 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
 				enable_extended_display_fifo = false;
 			} else {
 				/* SR17[6:0] */
-				fifo_max_depth = 128;
+				fifo_max_depth = 64;
 
 				/* SR16[5:0] */
 				fifo_threshold = 32;