[Openchrome-devel] drm-openchrome: Branch 'drm-next-3.19' - 2 commits - drivers/gpu/drm

[Kevin Brace]

 drivers/gpu/drm/openchrome/via_drv.c |   59 +++++++++++++++++++++++++----------
 drivers/gpu/drm/openchrome/via_drv.h |    4 +-
 2 files changed, 45 insertions(+), 18 deletions(-)

New commits:
commit 544222399bf6662bb618e229e8f42e345fb7e014
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Tue Feb 13 07:09:02 2018 -0800

    drm/openchrome: Version bumped to 3.0.73
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/openchrome/via_drv.h b/drivers/gpu/drm/openchrome/via_drv.h
index 119aa9aa46ac..5fc0f3c292eb 100644
--- a/drivers/gpu/drm/openchrome/via_drv.h
+++ b/drivers/gpu/drm/openchrome/via_drv.h
@@ -30,11 +30,11 @@
 #define DRIVER_AUTHOR       "OpenChrome Project"
 #define DRIVER_NAME         "openchrome"
 #define DRIVER_DESC         "OpenChrome DRM for VIA Technologies Chrome IGP"
-#define DRIVER_DATE         "20180204"
+#define DRIVER_DATE         "20180213"
 
 #define DRIVER_MAJOR		3
 #define DRIVER_MINOR		0
-#define DRIVER_PATCHLEVEL	72
+#define DRIVER_PATCHLEVEL	73
 
 #include <linux/module.h>
 
commit 6ef5766ac952a71d0d0ee03170bdc6babbadff70
Author: Kevin Brace <kevinbrace at gmx.com>
Date:   Tue Feb 13 07:04:16 2018 -0800

    drm/openchrome: Fix for chip_revision_info
    
    Starting with the newer PCIe generation Chrome IGP found in VX800,
    VX855, and VX900 chipsets, the PCI bus location of the device was
    changed from the earlier AGP generation Chrome IGP. There are
    situations where the device's PCI subvendor ID and subsystem ID need to
    be available to DRM, and this fix corrects the problem for the newer
    PCIe generation Chrome IGP.
    
    Signed-off-by: Kevin Brace <kevinbrace at gmx.com>

diff --git a/drivers/gpu/drm/openchrome/via_drv.c b/drivers/gpu/drm/openchrome/via_drv.c
index 9cc23a86d307..2e3ddb964d93 100644
--- a/drivers/gpu/drm/openchrome/via_drv.c
+++ b/drivers/gpu/drm/openchrome/via_drv.c
@@ -163,53 +163,78 @@ static void via_mmio_setup(struct via_device *dev_priv)
 static void chip_revision_info(struct drm_device *dev)
 {
 	struct via_device *dev_priv = dev->dev_private;
-	struct pci_bus *bus;
-	struct pci_dev *device;
+	struct pci_bus *bus = NULL;
 	u16 device_id, subsystem_vendor_id, subsystem_device_id;
 	u8 tmp;
+	int pci_bus;
+	u8 pci_device, pci_function;
 	int ret;
 
 	DRM_DEBUG_KMS("Entered %s.\n", __func__);
 
-	bus = pci_find_bus(0, 1);
-	if (!bus) {
-		goto pci_error;
+	/*
+	 * VX800, VX855, and VX900 chipsets have Chrome IGP
+	 * connected as Bus 0, Device 1 PCI device.
+	 */
+	if ((dev->pdev->device == PCI_DEVICE_ID_VIA_VT1122) ||
+		(dev->pdev->device == PCI_DEVICE_ID_VIA_VX875) ||
+		(dev->pdev->device == PCI_DEVICE_ID_VIA_VX900_VGA)) {
+
+		pci_bus = 0;
+		pci_device = 1;
+		pci_function = 0;
+
+	/*
+	 * For all other devices, Chrome IGP is connected as
+	 * Bus 1, Device 0 PCI Device.
+	 */
+	} else {
+		pci_bus = 1;
+		pci_device = 0;
+		pci_function = 0;
 	}
 
-	device = pci_get_slot(bus, PCI_DEVFN(0, 0));
-	if (!device) {
+	bus = pci_find_bus(0, pci_bus);
+	if (!bus) {
 		goto pci_error;
 	}
 
-	ret = pci_read_config_word(device, 0x02, &device_id);
+	ret = pci_bus_read_config_word(bus, PCI_DEVFN(pci_device,
+							pci_function),
+					PCI_DEVICE_ID,
+					&device_id);
 	if (ret) {
 		goto pci_error;
 	}
 
-	ret = pci_read_config_word(device, 0x2c,
+	ret = pci_bus_read_config_word(bus, PCI_DEVFN(pci_device,
+							pci_function),
+					PCI_SUBSYSTEM_VENDOR_ID,
 					&subsystem_vendor_id);
 	if (ret) {
 		goto pci_error;
 	}
 
-	ret = pci_read_config_word(device, 0x2e,
+	ret = pci_bus_read_config_word(bus, PCI_DEVFN(pci_device,
+							pci_function),
+					PCI_SUBSYSTEM_ID,
 					&subsystem_device_id);
 	if (ret) {
 		goto pci_error;
 	}
 
+	DRM_DEBUG_KMS("DRM Device ID: "
+			"0x%04x\n", dev->pdev->device);
 	DRM_DEBUG_KMS("Chrome IGP Device ID: "
-			"0x%04X\n", device_id);
+			"0x%04x\n", device_id);
 	DRM_DEBUG_KMS("Chrome IGP Subsystem Vendor ID: "
-			"0x%04X\n", subsystem_vendor_id);
+			"0x%04x\n", subsystem_vendor_id);
 	DRM_DEBUG_KMS("Chrome IGP Subsystem Device ID: "
-			"0x%04X\n", subsystem_device_id);
+			"0x%04x\n", subsystem_device_id);
 
 	switch (dev->pdev->device) {
-
-	/* Check the revision of CLE266 chipset. */
+	/* CLE266 Chipset */
 	case PCI_DEVICE_ID_VIA_CLE266:
-
 		/* CR4F only defined in CLE266.CX chipset. */
 		tmp = vga_rcrt(VGABASE, 0x4F);
 		vga_wcrt(VGABASE, 0x4F, 0x55);
@@ -259,7 +284,9 @@ static void chip_revision_info(struct drm_device *dev)
 		}
 
 		break;
+	/* VX855 / VX875 Chipset */
 	case PCI_DEVICE_ID_VIA_VX875:
+	/* VX900 Chipset */
 	case PCI_DEVICE_ID_VIA_VX900_VGA:
 		dev_priv->revision = vga_rseq(VGABASE, 0x3B);
 		break;