[Openchrome-devel] drm-openchrome: Branch 'drm-next-4.14' - 4 commits - drivers/gpu/drm
Kevin Brace
kevinbrace at kemper.freedesktop.org
Sun Jan 28 01:45:28 UTC 2018
drivers/gpu/drm/openchrome/via_crtc.c | 147 ++++++++++++++++++++++--------
drivers/gpu/drm/openchrome/via_disp_reg.h | 18 ++-
drivers/gpu/drm/openchrome/via_drv.h | 4
3 files changed, 125 insertions(+), 44 deletions(-)
New commits:
commit 062367c81ec6ad13b03e0c44ea20a1700979b017
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sat Jan 27 17:44:21 2018 -0800
drm/openchrome: Version bumped to 3.0.60
Added code to properly set IGA2 display FIFO for KM400 chipset.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_drv.h b/drivers/gpu/drm/openchrome/via_drv.h
index 6ffe92d9ba50..3890702c186a 100644
--- a/drivers/gpu/drm/openchrome/via_drv.h
+++ b/drivers/gpu/drm/openchrome/via_drv.h
@@ -30,11 +30,11 @@
#define DRIVER_AUTHOR "OpenChrome Project"
#define DRIVER_NAME "openchrome"
#define DRIVER_DESC "OpenChrome DRM for VIA Technologies Chrome IGP"
-#define DRIVER_DATE "20180126"
+#define DRIVER_DATE "20180127"
#define DRIVER_MAJOR 3
#define DRIVER_MINOR 0
-#define DRIVER_PATCHLEVEL 59
+#define DRIVER_PATCHLEVEL 60
#include <linux/module.h>
commit 3b10a8084b022570aa3e7c7fbe40b4ccdbed8e56
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sat Jan 27 17:42:39 2018 -0800
drm/openchrome: Set KM400 chipset IGA2 display FIFO when mode setting
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_crtc.c b/drivers/gpu/drm/openchrome/via_crtc.c
index 2b9e4219a0a2..ac5aef0e4862 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -687,6 +687,56 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
DRM_DEBUG_KMS("Entered %s.\n", __func__);
switch (dev->pdev->device) {
+ case PCI_DEVICE_ID_VIA_KM400:
+ if (mode->hdisplay >= 1600) {
+ /* CR68[7:4] */
+ iga->fifo_max_depth = 120;
+
+ /* CR68[3:0] */
+ iga->fifo_threshold = 44;
+
+ /* Enable IGA2 extended display FIFO. */
+ svga_wcrt_mask(VGABASE, 0x6a, BIT(5), BIT(5));
+ } else if (((mode->hdisplay > 1024) &&
+ (fb->format->depth == 32) &&
+ (dev_priv->vram_type <= VIA_MEM_DDR_333))
+ || ((mode->hdisplay == 1024) &&
+ (fb->format->depth == 32) &&
+ (dev_priv->vram_type <= VIA_MEM_DDR_200))) {
+ /* CR68[7:4] */
+ iga->fifo_max_depth = 104;
+
+ /* CR68[3:0] */
+ iga->fifo_threshold = 28;
+
+ /* Enable IGA2 extended display FIFO. */
+ svga_wcrt_mask(VGABASE, 0x6a, BIT(5), BIT(5));
+ } else if (((mode->hdisplay > 1280) &&
+ (fb->format->depth == 16) &&
+ (dev_priv->vram_type <= VIA_MEM_DDR_333))
+ || ((mode->hdisplay == 1280) &&
+ (fb->format->depth == 16) &&
+ (dev_priv->vram_type <= VIA_MEM_DDR_200))) {
+ /* CR68[7:4] */
+ iga->fifo_max_depth = 88;
+
+ /* CR68[3:0] */
+ iga->fifo_threshold = 44;
+
+ /* Enable IGA2 extended display FIFO. */
+ svga_wcrt_mask(VGABASE, 0x6a, BIT(5), BIT(5));
+ } else {
+ /* CR68[7:4] */
+ iga->fifo_max_depth = 56;
+
+ /* CR68[3:0] */
+ iga->fifo_threshold = 28;
+
+ /* Disable IGA2 extended display FIFO. */
+ svga_wcrt_mask(VGABASE, 0x6a, 0x00, BIT(5));
+ }
+
+ break;
case PCI_DEVICE_ID_VIA_K8M800:
iga->display_queue_expire_num = 0;
iga->fifo_high_threshold = 296;
@@ -1822,9 +1872,8 @@ via_iga2_crtc_mode_set(struct drm_crtc *crtc,
via_iga2_interlace_mode(VGABASE,
adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE);
- /* Load FIFO */
- if ((dev->pdev->device != PCI_DEVICE_ID_VIA_CLE266)
- && (dev->pdev->device != PCI_DEVICE_ID_VIA_KM400)) {
+ /* Load display FIFO parameters. */
+ if (dev->pdev->device != PCI_DEVICE_ID_VIA_CLE266) {
via_iga2_display_fifo_regs(dev, dev_priv, iga,
adjusted_mode, crtc->primary->fb);
} else if (adjusted_mode->hdisplay == 1024
commit 8248138a2cfbdaf7cbb7192a700264ea78da9bd7
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sat Jan 27 17:20:35 2018 -0800
drm/openchrome: Add fb parameter to via_iga*_display_fifo_regs
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_crtc.c b/drivers/gpu/drm/openchrome/via_crtc.c
index 7f084751858a..2b9e4219a0a2 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -532,7 +532,8 @@ via_load_vpit_regs(struct via_device *dev_priv)
static void via_iga1_display_fifo_regs(struct drm_device *dev,
struct via_device *dev_priv,
struct via_crtc *iga,
- struct drm_display_mode *mode)
+ struct drm_display_mode *mode,
+ struct drm_framebuffer *fb)
{
u32 reg_value;
@@ -678,7 +679,8 @@ static void via_iga1_display_fifo_regs(struct drm_device *dev,
static void via_iga2_display_fifo_regs(struct drm_device *dev,
struct via_device *dev_priv,
struct via_crtc *iga,
- struct drm_display_mode *mode)
+ struct drm_display_mode *mode,
+ struct drm_framebuffer *fb)
{
u32 reg_value;
@@ -1510,7 +1512,8 @@ via_iga1_crtc_mode_set(struct drm_crtc *crtc,
/* Load FIFO */
if (dev->pdev->device != PCI_DEVICE_ID_VIA_CLE266) {
- via_iga1_display_fifo_regs(dev, dev_priv, iga, adjusted_mode);
+ via_iga1_display_fifo_regs(dev, dev_priv, iga,
+ adjusted_mode, crtc->primary->fb);
} else if (adjusted_mode->hdisplay == 1024
&& adjusted_mode->vdisplay == 768) {
/* Update Patch Register */
@@ -1822,7 +1825,8 @@ via_iga2_crtc_mode_set(struct drm_crtc *crtc,
/* Load FIFO */
if ((dev->pdev->device != PCI_DEVICE_ID_VIA_CLE266)
&& (dev->pdev->device != PCI_DEVICE_ID_VIA_KM400)) {
- via_iga2_display_fifo_regs(dev, dev_priv, iga, adjusted_mode);
+ via_iga2_display_fifo_regs(dev, dev_priv, iga,
+ adjusted_mode, crtc->primary->fb);
} else if (adjusted_mode->hdisplay == 1024
&& adjusted_mode->vdisplay == 768) {
/* Update Patch Register */
commit d94eede1c862db9ecfc764d3bb0cb59f148f7ce5
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Sat Jan 27 17:12:53 2018 -0800
drm/openchrome: Code to set IGA2 display FIFO for the missing hardware
The code to set IGA2 display FIFO was missing for CLE266 and KM400
chipsets, and this was leading to mode setting issues after standby
resume.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/via_crtc.c b/drivers/gpu/drm/openchrome/via_crtc.c
index c08d68e3ea26..7f084751858a 100644
--- a/drivers/gpu/drm/openchrome/via_crtc.c
+++ b/drivers/gpu/drm/openchrome/via_crtc.c
@@ -764,30 +764,40 @@ static void via_iga2_display_fifo_regs(struct drm_device *dev,
break;
}
- /* If resolution > 1280x1024, expire length = 64, else
- expire length = 128 */
- if ((dev->pdev->device == PCI_DEVICE_ID_VIA_K8M800
- || dev->pdev->device == PCI_DEVICE_ID_VIA_CN700)
- && ((mode->hdisplay > 1280) && (mode->vdisplay > 1024)))
- iga->display_queue_expire_num = 16;
-
- /* Set IGA2 Display FIFO Depth Select */
- reg_value = IGA2_FIFO_DEPTH_SELECT_FORMULA(iga->fifo_max_depth);
- if (dev->pdev->device == PCI_DEVICE_ID_VIA_K8M800)
- reg_value--;
- load_value_to_registers(VGABASE, &iga->fifo_depth, reg_value);
-
- /* Set Display FIFO Threshold Select */
- reg_value = iga->fifo_threshold / 4;
- load_value_to_registers(VGABASE, &iga->threshold, reg_value);
-
- /* Set FIFO High Threshold Select */
- reg_value = iga->fifo_high_threshold / 4;
- load_value_to_registers(VGABASE, &iga->high_threshold, reg_value);
-
- /* Set Display Queue Expire Num */
- reg_value = iga->display_queue_expire_num / 4;
- load_value_to_registers(VGABASE, &iga->display_queue, reg_value);
+ if (dev->pdev->device == PCI_DEVICE_ID_VIA_KM400) {
+ /* Set IGA2 Display FIFO Depth Select */
+ reg_value = IGA2_FIFO_DEPTH_SELECT_FORMULA(iga->fifo_max_depth);
+ load_value_to_registers(VGABASE, &iga->fifo_depth, reg_value);
+
+ /* Set Display FIFO Threshold Select */
+ reg_value = iga->fifo_threshold / 4;
+ load_value_to_registers(VGABASE, &iga->threshold, reg_value);
+ } else {
+ /* If resolution > 1280x1024, expire length = 64, else
+ expire length = 128 */
+ if ((dev->pdev->device == PCI_DEVICE_ID_VIA_K8M800
+ || dev->pdev->device == PCI_DEVICE_ID_VIA_CN700)
+ && ((mode->hdisplay > 1280) && (mode->vdisplay > 1024)))
+ iga->display_queue_expire_num = 16;
+
+ /* Set IGA2 Display FIFO Depth Select */
+ reg_value = IGA2_FIFO_DEPTH_SELECT_FORMULA(iga->fifo_max_depth);
+ if (dev->pdev->device == PCI_DEVICE_ID_VIA_K8M800)
+ reg_value--;
+ load_value_to_registers(VGABASE, &iga->fifo_depth, reg_value);
+
+ /* Set Display FIFO Threshold Select */
+ reg_value = iga->fifo_threshold / 4;
+ load_value_to_registers(VGABASE, &iga->threshold, reg_value);
+
+ /* Set FIFO High Threshold Select */
+ reg_value = iga->fifo_high_threshold / 4;
+ load_value_to_registers(VGABASE, &iga->high_threshold, reg_value);
+
+ /* Set Display Queue Expire Num */
+ reg_value = iga->display_queue_expire_num / 4;
+ load_value_to_registers(VGABASE, &iga->display_queue, reg_value);
+ }
DRM_DEBUG_KMS("Exiting %s.\n", __func__);
}
@@ -1964,17 +1974,25 @@ via_crtc_init(struct drm_device *dev, int index)
iga->timings.vsync_end.regs = iga2_ver_sync_end;
/* Secondary FIFO setup */
- iga->high_threshold.count = ARRAY_SIZE(iga2_fifo_high_threshold_select);
- iga->high_threshold.regs = iga2_fifo_high_threshold_select;
+ if (dev->pdev->device == PCI_DEVICE_ID_VIA_KM400) {
+ iga->fifo_depth.count = ARRAY_SIZE(iga2_cle266_fifo_depth_select);
+ iga->fifo_depth.regs = iga2_cle266_fifo_depth_select;
- iga->threshold.count = ARRAY_SIZE(iga2_fifo_threshold_select);
- iga->threshold.regs = iga2_fifo_threshold_select;
+ iga->threshold.count = ARRAY_SIZE(iga2_cle266_fifo_threshold_select);
+ iga->threshold.regs = iga2_cle266_fifo_threshold_select;
+ } else {
+ iga->fifo_depth.count = ARRAY_SIZE(iga2_k8m800_fifo_depth_select);
+ iga->fifo_depth.regs = iga2_k8m800_fifo_depth_select;
+
+ iga->threshold.count = ARRAY_SIZE(iga2_k8m800_fifo_threshold_select);
+ iga->threshold.regs = iga2_k8m800_fifo_threshold_select;
- iga->display_queue.count = ARRAY_SIZE(iga2_display_queue_expire_num);
- iga->display_queue.regs = iga2_display_queue_expire_num;
+ iga->high_threshold.count = ARRAY_SIZE(iga2_fifo_high_threshold_select);
+ iga->high_threshold.regs = iga2_fifo_high_threshold_select;
- iga->fifo_depth.count = ARRAY_SIZE(iga2_fifo_depth_select);
- iga->fifo_depth.regs = iga2_fifo_depth_select;
+ iga->display_queue.count = ARRAY_SIZE(iga2_display_queue_expire_num);
+ iga->display_queue.regs = iga2_display_queue_expire_num;
+ }
iga->fetch.count = ARRAY_SIZE(iga2_fetch_count);
iga->fetch.regs = iga2_fetch_count;
diff --git a/drivers/gpu/drm/openchrome/via_disp_reg.h b/drivers/gpu/drm/openchrome/via_disp_reg.h
index 9b8e26805272..ada0880e8cfe 100644
--- a/drivers/gpu/drm/openchrome/via_disp_reg.h
+++ b/drivers/gpu/drm/openchrome/via_disp_reg.h
@@ -139,8 +139,13 @@ static struct vga_regset iga1_fifo_depth_select[] = {
{ VGA_SEQ_I, 0x17, 0, 7 }
};
-/* IGA2 FIFO Depth_Select */
-static struct vga_regset iga2_fifo_depth_select[] = {
+/* CLE266 and KM400 IGA2 FIFO Depth_Select */
+static struct vga_regset iga2_cle266_fifo_depth_select[] = {
+ { VGA_CRT_IC, 0x68, 4, 7 }
+};
+
+/* K8M800 or later IGA2 FIFO Depth_Select */
+static struct vga_regset iga2_k8m800_fifo_depth_select[] = {
{ VGA_CRT_IC, 0x68, 4, 7 },
{ VGA_CRT_IC, 0x94, 7, 7 },
{ VGA_CRT_IC, 0x95, 7, 7 }
@@ -152,8 +157,13 @@ static struct vga_regset iga1_fifo_threshold_select[] = {
{ VGA_SEQ_I, 0x16, 7, 7 }
};
-/* IGA2 FIFO Threshold Select */
-static struct vga_regset iga2_fifo_threshold_select[] = {
+/* CLE266 and KM400 IGA2 FIFO Threshold Select */
+static struct vga_regset iga2_cle266_fifo_threshold_select[] = {
+ { VGA_CRT_IC, 0x68, 0, 3 }
+};
+
+/* K8M800 or later IGA2 FIFO Threshold Select */
+static struct vga_regset iga2_k8m800_fifo_threshold_select[] = {
{ VGA_CRT_IC, 0x68, 0, 3 },
{ VGA_CRT_IC, 0x95, 4, 6 }
};
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