[openchrome-devel] drm-openchrome: Branch 'drm-next-4.21' - 5 commits - drivers/gpu/drm
Kevin Brace
kevinbrace at kemper.freedesktop.org
Tue Jan 8 02:34:35 UTC 2019
drivers/gpu/drm/openchrome/Makefile | 1
drivers/gpu/drm/openchrome/openchrome_drv.c | 505 ----------------------
drivers/gpu/drm/openchrome/openchrome_drv.h | 17
drivers/gpu/drm/openchrome/openchrome_init.c | 607 +++++++++++++++++++++++++++
drivers/gpu/drm/openchrome/openchrome_pm.c | 379 ++++++----------
5 files changed, 783 insertions(+), 726 deletions(-)
New commits:
commit 9ad811be05558aaedcc8598efe6ad12ac884fa79
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Mon Jan 7 18:33:33 2019 -0800
drm/openchrome: Version bumped to 3.1.2
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/openchrome_drv.h b/drivers/gpu/drm/openchrome/openchrome_drv.h
index f1ee5790fd2f..cfcc5e71afcf 100644
--- a/drivers/gpu/drm/openchrome/openchrome_drv.h
+++ b/drivers/gpu/drm/openchrome/openchrome_drv.h
@@ -52,7 +52,7 @@
#define DRIVER_MAJOR 3
#define DRIVER_MINOR 1
-#define DRIVER_PATCHLEVEL 1
+#define DRIVER_PATCHLEVEL 2
#define DRIVER_NAME "openchrome"
#define DRIVER_DESC "OpenChrome DRM for VIA Technologies Chrome IGP"
#define DRIVER_DATE "20190107"
commit fa41506ff0ccbd70dcaff47151fa116a877e2c35
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Mon Jan 7 18:31:30 2019 -0800
drm/openchrome: KMS is now always turned on
There is really no reason to make this selectable.
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/openchrome_drv.c b/drivers/gpu/drm/openchrome/openchrome_drv.c
index 7f45a8e8f085..62e31e357890 100644
--- a/drivers/gpu/drm/openchrome/openchrome_drv.c
+++ b/drivers/gpu/drm/openchrome/openchrome_drv.c
@@ -36,10 +36,6 @@
#include "openchrome_drv.h"
-int via_modeset = 1;
-
-MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
-module_param_named(modeset, via_modeset, int, 0400);
int via_hdmi_audio = 0;
@@ -285,7 +281,8 @@ static const struct file_operations via_driver_fops = {
static struct drm_driver via_driver = {
.driver_features = DRIVER_USE_AGP | DRIVER_HAVE_IRQ |
- DRIVER_IRQ_SHARED | DRIVER_GEM,
+ DRIVER_IRQ_SHARED | DRIVER_GEM |
+ DRIVER_MODESET,
.load = via_driver_load,
.unload = via_driver_unload,
.lastclose = via_driver_lastclose,
@@ -344,10 +341,6 @@ static int __init via_init(void)
via_driver.num_ioctls = via_max_ioctl;
- if (via_modeset) {
- via_driver.driver_features |= DRIVER_MODESET;
- }
-
ret = pci_register_driver(&via_pci_driver);
DRM_DEBUG_KMS("Exiting %s.\n", __func__);
commit 4832328d62395712edf045cf11f1ced353f6ba13
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Mon Jan 7 18:30:01 2019 -0800
drm/openchrome: Move standby and resume code into openchrome_pm.c
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/openchrome_drv.c b/drivers/gpu/drm/openchrome/openchrome_drv.c
index 5dad75d5e760..7f45a8e8f085 100644
--- a/drivers/gpu/drm/openchrome/openchrome_drv.c
+++ b/drivers/gpu/drm/openchrome/openchrome_drv.c
@@ -26,8 +26,9 @@
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
+
+
#include <linux/module.h>
-#include <linux/console.h>
#include <drm/drmP.h>
#include <drm/via_drm.h>
@@ -267,132 +268,9 @@ static void via_driver_lastclose(struct drm_device *dev)
DRM_DEBUG_KMS("Exiting %s.\n", __func__);
}
-static int via_pm_ops_suspend(struct device *dev)
-{
- struct pci_dev *pdev = to_pci_dev(dev);
- struct drm_device *drm_dev = pci_get_drvdata(pdev);
- struct openchrome_drm_private *dev_private = drm_dev->dev_private;
-
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- console_lock();
- drm_fb_helper_set_suspend(&dev_private->via_fbdev->helper,
- true);
-
- /*
- * Frame Buffer Size Control register (SR14) and GTI registers
- * (SR66 through SR6F) need to be saved and restored upon standby
- * resume or can lead to a display corruption issue. These registers
- * are only available on VX800, VX855, and VX900 chipsets. This bug
- * was observed on VIA EPIA-M830 mainboard.
- */
- if ((drm_dev->pdev->device == PCI_DEVICE_ID_VIA_VT1122) ||
- (drm_dev->pdev->device == PCI_DEVICE_ID_VIA_VX875) ||
- (drm_dev->pdev->device == PCI_DEVICE_ID_VIA_VX900_VGA)) {
- dev_private->saved_sr14 = vga_rseq(VGABASE, 0x14);
-
- dev_private->saved_sr66 = vga_rseq(VGABASE, 0x66);
- dev_private->saved_sr67 = vga_rseq(VGABASE, 0x67);
- dev_private->saved_sr68 = vga_rseq(VGABASE, 0x68);
- dev_private->saved_sr69 = vga_rseq(VGABASE, 0x69);
- dev_private->saved_sr6a = vga_rseq(VGABASE, 0x6a);
- dev_private->saved_sr6b = vga_rseq(VGABASE, 0x6b);
- dev_private->saved_sr6c = vga_rseq(VGABASE, 0x6c);
- dev_private->saved_sr6d = vga_rseq(VGABASE, 0x6d);
- dev_private->saved_sr6e = vga_rseq(VGABASE, 0x6e);
- dev_private->saved_sr6f = vga_rseq(VGABASE, 0x6f);
- }
-
- /* 3X5.3B through 3X5.3F are scratch pad registers.
- * They are important for FP detection.
- * Their values need to be saved because they get lost
- * when resuming from standby. */
- dev_private->saved_cr3b = vga_rcrt(VGABASE, 0x3b);
- dev_private->saved_cr3c = vga_rcrt(VGABASE, 0x3c);
- dev_private->saved_cr3d = vga_rcrt(VGABASE, 0x3d);
- dev_private->saved_cr3e = vga_rcrt(VGABASE, 0x3e);
- dev_private->saved_cr3f = vga_rcrt(VGABASE, 0x3f);
-
- console_unlock();
-
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
- return 0;
-}
-
-static int via_pm_ops_resume(struct device *dev)
-{
- struct pci_dev *pdev = to_pci_dev(dev);
- struct drm_device *drm_dev = pci_get_drvdata(pdev);
- struct openchrome_drm_private *dev_private =
- drm_dev->dev_private;
- void __iomem *regs = ioport_map(0x3c0, 100);
- u8 val;
-
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- console_lock();
-
- val = ioread8(regs + 0x03);
- iowrite8(val | 0x1, regs + 0x03);
- val = ioread8(regs + 0x0C);
- iowrite8(val | 0x1, regs + 0x02);
-
- /* Unlock Extended IO Space. */
- iowrite8(0x10, regs + 0x04);
- iowrite8(0x01, regs + 0x05);
- /* Unlock CRTC register protect. */
- iowrite8(0x47, regs + 0x14);
-
- /* Enable MMIO. */
- iowrite8(0x1a, regs + 0x04);
- val = ioread8(regs + 0x05);
- iowrite8(val | 0x38, regs + 0x05);
-
- /*
- * Frame Buffer Size Control register (SR14) and GTI registers
- * (SR66 through SR6F) need to be saved and restored upon standby
- * resume or can lead to a display corruption issue. These registers
- * are only available on VX800, VX855, and VX900 chipsets. This bug
- * was observed on VIA EPIA-M830 mainboard.
- */
- if ((drm_dev->pdev->device == PCI_DEVICE_ID_VIA_VT1122) ||
- (drm_dev->pdev->device == PCI_DEVICE_ID_VIA_VX875) ||
- (drm_dev->pdev->device == PCI_DEVICE_ID_VIA_VX900_VGA)) {
- vga_wseq(VGABASE, 0x14, dev_private->saved_sr14);
-
- vga_wseq(VGABASE, 0x66, dev_private->saved_sr66);
- vga_wseq(VGABASE, 0x67, dev_private->saved_sr67);
- vga_wseq(VGABASE, 0x68, dev_private->saved_sr68);
- vga_wseq(VGABASE, 0x69, dev_private->saved_sr69);
- vga_wseq(VGABASE, 0x6a, dev_private->saved_sr6a);
- vga_wseq(VGABASE, 0x6b, dev_private->saved_sr6b);
- vga_wseq(VGABASE, 0x6c, dev_private->saved_sr6c);
- vga_wseq(VGABASE, 0x6d, dev_private->saved_sr6d);
- vga_wseq(VGABASE, 0x6e, dev_private->saved_sr6e);
- vga_wseq(VGABASE, 0x6f, dev_private->saved_sr6f);
- }
-
- /* 3X5.3B through 3X5.3F are scratch pad registers.
- * They are important for FP detection.
- * Their values need to be restored because they are undefined
- * after resuming from standby. */
- vga_wcrt(VGABASE, 0x3b, dev_private->saved_cr3b);
- vga_wcrt(VGABASE, 0x3c, dev_private->saved_cr3c);
- vga_wcrt(VGABASE, 0x3d, dev_private->saved_cr3d);
- vga_wcrt(VGABASE, 0x3e, dev_private->saved_cr3e);
- vga_wcrt(VGABASE, 0x3f, dev_private->saved_cr3f);
-
- drm_helper_resume_force_mode(drm_dev);
- drm_fb_helper_set_suspend(&dev_private->via_fbdev->helper, false);
- console_unlock();
-
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
- return 0;
-}
-
-static const struct dev_pm_ops via_dev_pm_ops = {
- .suspend = via_pm_ops_suspend,
- .resume = via_pm_ops_resume,
+static const struct dev_pm_ops openchrome_dev_pm_ops = {
+ .suspend = openchrome_dev_pm_ops_suspend,
+ .resume = openchrome_dev_pm_ops_resume,
};
static const struct file_operations via_driver_fops = {
@@ -455,7 +333,7 @@ static struct pci_driver via_pci_driver = {
.id_table = via_pci_table,
.probe = via_pci_probe,
.remove = via_pci_remove,
- .driver.pm = &via_dev_pm_ops,
+ .driver.pm = &openchrome_dev_pm_ops,
};
static int __init via_init(void)
diff --git a/drivers/gpu/drm/openchrome/openchrome_drv.h b/drivers/gpu/drm/openchrome/openchrome_drv.h
index 6a16169c4e85..f1ee5790fd2f 100644
--- a/drivers/gpu/drm/openchrome/openchrome_drv.h
+++ b/drivers/gpu/drm/openchrome/openchrome_drv.h
@@ -277,6 +277,9 @@ int openchrome_device_init(struct openchrome_drm_private *dev_private);
extern void via_engine_init(struct drm_device *dev);
+int openchrome_dev_pm_ops_suspend(struct device *dev);
+int openchrome_dev_pm_ops_resume(struct device *dev);
+
extern int via_vram_detect(struct openchrome_drm_private *dev_private);
extern int openchrome_vram_init(
struct openchrome_drm_private *dev_private);
diff --git a/drivers/gpu/drm/openchrome/openchrome_pm.c b/drivers/gpu/drm/openchrome/openchrome_pm.c
index 74b59f024d48..d3b79d180ce3 100644
--- a/drivers/gpu/drm/openchrome/openchrome_pm.c
+++ b/drivers/gpu/drm/openchrome/openchrome_pm.c
@@ -1,28 +1,169 @@
/*
- * Copyright 2012 James Simmons <jsimmons at infradead.org>. All Rights Reserved.
+ * Copyright © 2017 Kevin Brace
*
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sub license,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
*
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
+ * The above copyright notice and this permission notice (including
+ * the next paragraph) shall be included in all copies or substantial
+ * portions of the Software.
*
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
+/*
+ * Author(s):
+ *
+ * Kevin Brace <kevinbrace at gmx.com>
+ */
-#include "drmP.h"
+
+#include <linux/console.h>
#include "openchrome_drv.h"
+int openchrome_dev_pm_ops_suspend(struct device *dev)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct drm_device *drm_dev = pci_get_drvdata(pdev);
+ struct openchrome_drm_private *dev_private = drm_dev->dev_private;
+
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ console_lock();
+ drm_fb_helper_set_suspend(&dev_private->via_fbdev->helper,
+ true);
+
+ /*
+ * Frame Buffer Size Control register (SR14) and GTI registers
+ * (SR66 through SR6F) need to be saved and restored upon standby
+ * resume or can lead to a display corruption issue. These registers
+ * are only available on VX800, VX855, and VX900 chipsets. This bug
+ * was observed on VIA Embedded EPIA-M830 mainboard.
+ */
+ if ((drm_dev->pdev->device == PCI_DEVICE_ID_VIA_VT1122) ||
+ (drm_dev->pdev->device == PCI_DEVICE_ID_VIA_VX875) ||
+ (drm_dev->pdev->device == PCI_DEVICE_ID_VIA_VX900_VGA)) {
+ dev_private->saved_sr14 = vga_rseq(VGABASE, 0x14);
+
+ dev_private->saved_sr66 = vga_rseq(VGABASE, 0x66);
+ dev_private->saved_sr67 = vga_rseq(VGABASE, 0x67);
+ dev_private->saved_sr68 = vga_rseq(VGABASE, 0x68);
+ dev_private->saved_sr69 = vga_rseq(VGABASE, 0x69);
+ dev_private->saved_sr6a = vga_rseq(VGABASE, 0x6a);
+ dev_private->saved_sr6b = vga_rseq(VGABASE, 0x6b);
+ dev_private->saved_sr6c = vga_rseq(VGABASE, 0x6c);
+ dev_private->saved_sr6d = vga_rseq(VGABASE, 0x6d);
+ dev_private->saved_sr6e = vga_rseq(VGABASE, 0x6e);
+ dev_private->saved_sr6f = vga_rseq(VGABASE, 0x6f);
+ }
+
+ /*
+ * 3X5.3B through 3X5.3F are scratch pad registers.
+ * They are important for FP detection.
+ * Their values need to be saved because they get lost
+ * when resuming from standby.
+ */
+ dev_private->saved_cr3b = vga_rcrt(VGABASE, 0x3b);
+ dev_private->saved_cr3c = vga_rcrt(VGABASE, 0x3c);
+ dev_private->saved_cr3d = vga_rcrt(VGABASE, 0x3d);
+ dev_private->saved_cr3e = vga_rcrt(VGABASE, 0x3e);
+ dev_private->saved_cr3f = vga_rcrt(VGABASE, 0x3f);
+
+ console_unlock();
+
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+ return 0;
+}
+
+int openchrome_dev_pm_ops_resume(struct device *dev)
+{
+ struct pci_dev *pdev = to_pci_dev(dev);
+ struct drm_device *drm_dev = pci_get_drvdata(pdev);
+ struct openchrome_drm_private *dev_private =
+ drm_dev->dev_private;
+ void __iomem *regs = ioport_map(0x3c0, 100);
+ u8 val;
+
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ console_lock();
+
+ val = ioread8(regs + 0x03);
+ iowrite8(val | 0x1, regs + 0x03);
+ val = ioread8(regs + 0x0C);
+ iowrite8(val | 0x1, regs + 0x02);
+
+ /*
+ * Unlock Extended IO Space.
+ */
+ iowrite8(0x10, regs + 0x04);
+ iowrite8(0x01, regs + 0x05);
+
+ /*
+ * Unlock CRTC register protect.
+ */
+ iowrite8(0x47, regs + 0x14);
+
+ /*
+ * Enable MMIO.
+ */
+ iowrite8(0x1a, regs + 0x04);
+ val = ioread8(regs + 0x05);
+ iowrite8(val | 0x38, regs + 0x05);
+
+ /*
+ * Frame Buffer Size Control register (SR14) and GTI registers
+ * (SR66 through SR6F) need to be saved and restored upon standby
+ * resume or can lead to a display corruption issue. These registers
+ * are only available on VX800, VX855, and VX900 chipsets. This bug
+ * was observed on VIA Embedded EPIA-M830 mainboard.
+ */
+ if ((drm_dev->pdev->device == PCI_DEVICE_ID_VIA_VT1122) ||
+ (drm_dev->pdev->device == PCI_DEVICE_ID_VIA_VX875) ||
+ (drm_dev->pdev->device == PCI_DEVICE_ID_VIA_VX900_VGA)) {
+ vga_wseq(VGABASE, 0x14, dev_private->saved_sr14);
+
+ vga_wseq(VGABASE, 0x66, dev_private->saved_sr66);
+ vga_wseq(VGABASE, 0x67, dev_private->saved_sr67);
+ vga_wseq(VGABASE, 0x68, dev_private->saved_sr68);
+ vga_wseq(VGABASE, 0x69, dev_private->saved_sr69);
+ vga_wseq(VGABASE, 0x6a, dev_private->saved_sr6a);
+ vga_wseq(VGABASE, 0x6b, dev_private->saved_sr6b);
+ vga_wseq(VGABASE, 0x6c, dev_private->saved_sr6c);
+ vga_wseq(VGABASE, 0x6d, dev_private->saved_sr6d);
+ vga_wseq(VGABASE, 0x6e, dev_private->saved_sr6e);
+ vga_wseq(VGABASE, 0x6f, dev_private->saved_sr6f);
+ }
+
+ /*
+ * 3X5.3B through 3X5.3F are scratch pad registers.
+ * They are important for FP detection.
+ * Their values need to be restored because they are undefined
+ * after resuming from standby.
+ */
+ vga_wcrt(VGABASE, 0x3b, dev_private->saved_cr3b);
+ vga_wcrt(VGABASE, 0x3c, dev_private->saved_cr3c);
+ vga_wcrt(VGABASE, 0x3d, dev_private->saved_cr3d);
+ vga_wcrt(VGABASE, 0x3e, dev_private->saved_cr3e);
+ vga_wcrt(VGABASE, 0x3f, dev_private->saved_cr3f);
+
+ drm_helper_resume_force_mode(drm_dev);
+ drm_fb_helper_set_suspend(&dev_private->via_fbdev->helper, false);
+ console_unlock();
+
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+ return 0;
+}
commit 7bdaed51e1ef1d63fe1918eba71a2127502252da
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Mon Jan 7 17:38:40 2019 -0800
drm/openchrome: Move engine initialization code into openchrome_init.c
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/openchrome_init.c b/drivers/gpu/drm/openchrome/openchrome_init.c
index dd3807ad2f40..5c1f25317078 100644
--- a/drivers/gpu/drm/openchrome/openchrome_init.c
+++ b/drivers/gpu/drm/openchrome/openchrome_init.c
@@ -384,3 +384,224 @@ exit:
DRM_DEBUG_KMS("Exiting %s.\n", __func__);
return ret;
}
+
+static void via_init_2d(
+ struct openchrome_drm_private *dev_private,
+ int pci_device)
+{
+ int i;
+
+ for (i = 0x04; i < 0x5c; i += 4)
+ VIA_WRITE(i, 0x0);
+
+ /* For 410 chip*/
+ if (pci_device == PCI_DEVICE_ID_VIA_VX900_VGA)
+ VIA_WRITE(0x60, 0x0);
+}
+
+static void via_init_3d(
+ struct openchrome_drm_private *dev_private)
+{
+ unsigned long texture_stage;
+ int i;
+
+ VIA_WRITE(VIA_REG_TRANSET, 0x00010000);
+ for (i = 0; i <= 0x9A; i++)
+ VIA_WRITE(VIA_REG_TRANSPACE, i << 24);
+
+ /* guardband clipping default setting */
+ VIA_WRITE(VIA_REG_TRANSPACE, (0x88 << 24) | 0x00001ed0);
+ VIA_WRITE(VIA_REG_TRANSPACE, (0x89 << 24) | 0x00000800);
+
+ /* Initial Texture Stage Setting */
+ for (texture_stage = 0; texture_stage <= 0xf; texture_stage++) {
+ VIA_WRITE(VIA_REG_TRANSET, (0x00020000 | 0x00000000 |
+ (texture_stage & 0xf) << 24));
+ for (i = 0 ; i <= 0x30 ; i++)
+ VIA_WRITE(VIA_REG_TRANSPACE, i << 24);
+ }
+
+ /* Initial Texture Sampler Setting */
+ for (texture_stage = 0; texture_stage <= 0xf; texture_stage++) {
+ VIA_WRITE(VIA_REG_TRANSET, (0x00020000 | 0x20000000 |
+ (texture_stage & 0x10) << 24));
+ for (i = 0; i <= 0x36; i++)
+ VIA_WRITE(VIA_REG_TRANSPACE, i << 24);
+ }
+
+ VIA_WRITE(VIA_REG_TRANSET, (0x00020000 | 0xfe000000));
+ for (i = 0 ; i <= 0x13 ; i++)
+ VIA_WRITE(VIA_REG_TRANSPACE, i << 24);
+
+ /* degamma table */
+ VIA_WRITE(VIA_REG_TRANSET, (0x00030000 | 0x15000000));
+ VIA_WRITE(VIA_REG_TRANSPACE, (0x40000000 | (30 << 20) | (15 << 10) | (5)));
+ VIA_WRITE(VIA_REG_TRANSPACE, ((119 << 20) | (81 << 10) | (52)));
+ VIA_WRITE(VIA_REG_TRANSPACE, ((283 << 20) | (219 << 10) | (165)));
+ VIA_WRITE(VIA_REG_TRANSPACE, ((535 << 20) | (441 << 10) | (357)));
+ VIA_WRITE(VIA_REG_TRANSPACE, ((119 << 20) | (884 << 20) | (757 << 10) | (640)));
+
+ /* gamma table */
+ VIA_WRITE(VIA_REG_TRANSET, (0x00030000 | 0x17000000));
+ VIA_WRITE(VIA_REG_TRANSPACE, (0x40000000 | (13 << 20) | (13 << 10) | (13)));
+ VIA_WRITE(VIA_REG_TRANSPACE, (0x40000000 | (26 << 20) | (26 << 10) | (26)));
+ VIA_WRITE(VIA_REG_TRANSPACE, (0x40000000 | (39 << 20) | (39 << 10) | (39)));
+ VIA_WRITE(VIA_REG_TRANSPACE, ((51 << 20) | (51 << 10) | (51)));
+ VIA_WRITE(VIA_REG_TRANSPACE, ((71 << 20) | (71 << 10) | (71)));
+ VIA_WRITE(VIA_REG_TRANSPACE, (87 << 20) | (87 << 10) | (87));
+ VIA_WRITE(VIA_REG_TRANSPACE, (113 << 20) | (113 << 10) | (113));
+ VIA_WRITE(VIA_REG_TRANSPACE, (135 << 20) | (135 << 10) | (135));
+ VIA_WRITE(VIA_REG_TRANSPACE, (170 << 20) | (170 << 10) | (170));
+ VIA_WRITE(VIA_REG_TRANSPACE, (199 << 20) | (199 << 10) | (199));
+ VIA_WRITE(VIA_REG_TRANSPACE, (246 << 20) | (246 << 10) | (246));
+ VIA_WRITE(VIA_REG_TRANSPACE, (284 << 20) | (284 << 10) | (284));
+ VIA_WRITE(VIA_REG_TRANSPACE, (317 << 20) | (317 << 10) | (317));
+ VIA_WRITE(VIA_REG_TRANSPACE, (347 << 20) | (347 << 10) | (347));
+ VIA_WRITE(VIA_REG_TRANSPACE, (373 << 20) | (373 << 10) | (373));
+ VIA_WRITE(VIA_REG_TRANSPACE, (398 << 20) | (398 << 10) | (398));
+ VIA_WRITE(VIA_REG_TRANSPACE, (442 << 20) | (442 << 10) | (442));
+ VIA_WRITE(VIA_REG_TRANSPACE, (481 << 20) | (481 << 10) | (481));
+ VIA_WRITE(VIA_REG_TRANSPACE, (517 << 20) | (517 << 10) | (517));
+ VIA_WRITE(VIA_REG_TRANSPACE, (550 << 20) | (550 << 10) | (550));
+ VIA_WRITE(VIA_REG_TRANSPACE, (609 << 20) | (609 << 10) | (609));
+ VIA_WRITE(VIA_REG_TRANSPACE, (662 << 20) | (662 << 10) | (662));
+ VIA_WRITE(VIA_REG_TRANSPACE, (709 << 20) | (709 << 10) | (709));
+ VIA_WRITE(VIA_REG_TRANSPACE, (753 << 20) | (753 << 10) | (753));
+ VIA_WRITE(VIA_REG_TRANSPACE, (794 << 20) | (794 << 10) | (794));
+ VIA_WRITE(VIA_REG_TRANSPACE, (832 << 20) | (832 << 10) | (832));
+ VIA_WRITE(VIA_REG_TRANSPACE, (868 << 20) | (868 << 10) | (868));
+ VIA_WRITE(VIA_REG_TRANSPACE, (902 << 20) | (902 << 10) | (902));
+ VIA_WRITE(VIA_REG_TRANSPACE, (934 << 20) | (934 << 10) | (934));
+ VIA_WRITE(VIA_REG_TRANSPACE, (966 << 20) | (966 << 10) | (966));
+ VIA_WRITE(VIA_REG_TRANSPACE, (996 << 20) | (996 << 10) | (996));
+
+ /* Initialize INV_ParaSubType_TexPa */
+ VIA_WRITE(VIA_REG_TRANSET, (0x00030000 | 0x00000000));
+ for (i = 0; i < 16; i++)
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x00000000);
+
+ /* Initialize INV_ParaSubType_4X4Cof */
+ VIA_WRITE(VIA_REG_TRANSET, (0x00030000 | 0x11000000));
+ for (i = 0; i < 32; i++)
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x00000000);
+
+ /* Initialize INV_ParaSubType_StipPal */
+ VIA_WRITE(VIA_REG_TRANSET, (0x00030000 | 0x14000000));
+ for (i = 0; i < (5 + 3); i++)
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x00000000);
+
+ /* primitive setting & vertex format */
+ VIA_WRITE(VIA_REG_TRANSET, (0x00040000));
+ for (i = 0; i <= 0x62; i++)
+ VIA_WRITE(VIA_REG_TRANSPACE, (i << 24));
+
+ /* c2s clamping value for screen coordinate */
+ VIA_WRITE(VIA_REG_TRANSPACE, (0x50 << 24) | 0x00000000);
+ VIA_WRITE(VIA_REG_TRANSPACE, (0x51 << 24) | 0x00000000);
+ VIA_WRITE(VIA_REG_TRANSPACE, (0x52 << 24) | 0x00147fff);
+
+ /* ParaType 0xFE - Configure and Misc Setting */
+ VIA_WRITE(VIA_REG_TRANSET, (0x00fe0000));
+ for (i = 0; i <= 0x47; i++)
+ VIA_WRITE(VIA_REG_TRANSPACE, (i << 24));
+
+ /* ParaType 0x11 - Frame Buffer Auto-Swapping and Command Regulator */
+ VIA_WRITE(VIA_REG_TRANSET, (0x00110000));
+ for (i = 0; i <= 0x20; i++)
+ VIA_WRITE(VIA_REG_TRANSPACE, (i << 24));
+
+ VIA_WRITE(VIA_REG_TRANSET, 0x00fe0000);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x4000840f);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x47000404);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x44000000);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x46000005);
+
+ /* setting Misconfig */
+ VIA_WRITE(VIA_REG_TRANSET, 0x00fe0000);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x00001004);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x08000249);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x0a0002c9);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x0b0002fb);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x0c000000);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x0d0002cb);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x0e000009);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x10000049);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x110002ff);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x12000008);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x130002db);
+}
+
+static void via_init_vq(struct openchrome_drm_private *dev_private)
+{
+ unsigned long vq_start_addr, vq_end_addr, vqlen;
+ unsigned long vqstartl, vqendl, vqstart_endh;
+ struct ttm_buffer_object *bo = dev_private->vq.bo;
+
+ if (!bo)
+ return;
+
+ vq_start_addr = bo->offset;
+ vq_end_addr = vq_start_addr + bo->mem.size - 1;
+ vqstartl = 0x70000000 | (vq_start_addr & 0xFFFFFF);
+ vqendl = 0x71000000 | (vq_end_addr & 0xFFFFFF);
+ vqstart_endh = 0x72000000 | ((vq_start_addr & 0xFF000000) >> 24) |
+ ((vq_end_addr & 0xFF000000) >> 16);
+ vqlen = 0x73000000 | (bo->mem.size >> 3);
+
+ VIA_WRITE(0x41c, 0x00100000);
+ VIA_WRITE(0x420, vqstart_endh);
+ VIA_WRITE(0x420, vqstartl);
+ VIA_WRITE(0x420, vqendl);
+ VIA_WRITE(0x420, vqlen);
+ VIA_WRITE(0x420, 0x74301001);
+ VIA_WRITE(0x420, 0x00000000);
+}
+
+static void via_init_pcie_gart_table(
+ struct openchrome_drm_private *dev_private,
+ struct pci_dev *pdev)
+{
+ struct ttm_buffer_object *bo = dev_private->gart.bo;
+ u8 value;
+
+ if (!pci_is_pcie(pdev) || !bo)
+ return;
+
+ /* enable gtt write */
+ svga_wseq_mask(VGABASE, 0x6C, 0x00, BIT(7));
+
+ /* set the base address of gart table */
+ value = (bo->offset & 0xff000) >> 12;
+ vga_wseq(VGABASE, 0x6A, value);
+
+ value = (bo->offset & 0xff000) >> 20;
+ vga_wseq(VGABASE, 0x6B, value);
+
+ value = vga_rseq(VGABASE, 0x6C);
+ value |= ((bo->offset >> 28) & 0x01);
+ vga_wseq(VGABASE, 0x6C, value);
+
+ /* flush the gtt cache */
+ svga_wseq_mask(VGABASE, 0x6F, BIT(7), BIT(7));
+
+ /* disable the gtt write */
+ svga_wseq_mask(VGABASE, 0x6C, BIT(7), BIT(7));
+}
+
+/* This function does:
+ * 1. Command buffer allocation
+ * 2. hw engine intialization:2D;3D;VQ
+ * 3. Ring Buffer mechanism setup
+ */
+void via_engine_init(struct drm_device *dev)
+{
+ struct openchrome_drm_private *dev_private = dev->dev_private;
+
+ /* initial engines */
+ via_init_2d(dev_private, dev->pdev->device);
+ via_init_3d(dev_private);
+ via_init_vq(dev_private);
+
+ /* pcie gart table setup */
+ via_init_pcie_gart_table(dev_private, dev->pdev);
+}
diff --git a/drivers/gpu/drm/openchrome/openchrome_pm.c b/drivers/gpu/drm/openchrome/openchrome_pm.c
index 8af8ae7c7543..74b59f024d48 100644
--- a/drivers/gpu/drm/openchrome/openchrome_pm.c
+++ b/drivers/gpu/drm/openchrome/openchrome_pm.c
@@ -26,223 +26,3 @@
#include "openchrome_drv.h"
-static void via_init_2d(
- struct openchrome_drm_private *dev_private,
- int pci_device)
-{
- int i;
-
- for (i = 0x04; i < 0x5c; i += 4)
- VIA_WRITE(i, 0x0);
-
- /* For 410 chip*/
- if (pci_device == PCI_DEVICE_ID_VIA_VX900_VGA)
- VIA_WRITE(0x60, 0x0);
-}
-
-static void via_init_3d(
- struct openchrome_drm_private *dev_private)
-{
- unsigned long texture_stage;
- int i;
-
- VIA_WRITE(VIA_REG_TRANSET, 0x00010000);
- for (i = 0; i <= 0x9A; i++)
- VIA_WRITE(VIA_REG_TRANSPACE, i << 24);
-
- /* guardband clipping default setting */
- VIA_WRITE(VIA_REG_TRANSPACE, (0x88 << 24) | 0x00001ed0);
- VIA_WRITE(VIA_REG_TRANSPACE, (0x89 << 24) | 0x00000800);
-
- /* Initial Texture Stage Setting */
- for (texture_stage = 0; texture_stage <= 0xf; texture_stage++) {
- VIA_WRITE(VIA_REG_TRANSET, (0x00020000 | 0x00000000 |
- (texture_stage & 0xf) << 24));
- for (i = 0 ; i <= 0x30 ; i++)
- VIA_WRITE(VIA_REG_TRANSPACE, i << 24);
- }
-
- /* Initial Texture Sampler Setting */
- for (texture_stage = 0; texture_stage <= 0xf; texture_stage++) {
- VIA_WRITE(VIA_REG_TRANSET, (0x00020000 | 0x20000000 |
- (texture_stage & 0x10) << 24));
- for (i = 0; i <= 0x36; i++)
- VIA_WRITE(VIA_REG_TRANSPACE, i << 24);
- }
-
- VIA_WRITE(VIA_REG_TRANSET, (0x00020000 | 0xfe000000));
- for (i = 0 ; i <= 0x13 ; i++)
- VIA_WRITE(VIA_REG_TRANSPACE, i << 24);
-
- /* degamma table */
- VIA_WRITE(VIA_REG_TRANSET, (0x00030000 | 0x15000000));
- VIA_WRITE(VIA_REG_TRANSPACE, (0x40000000 | (30 << 20) | (15 << 10) | (5)));
- VIA_WRITE(VIA_REG_TRANSPACE, ((119 << 20) | (81 << 10) | (52)));
- VIA_WRITE(VIA_REG_TRANSPACE, ((283 << 20) | (219 << 10) | (165)));
- VIA_WRITE(VIA_REG_TRANSPACE, ((535 << 20) | (441 << 10) | (357)));
- VIA_WRITE(VIA_REG_TRANSPACE, ((119 << 20) | (884 << 20) | (757 << 10) | (640)));
-
- /* gamma table */
- VIA_WRITE(VIA_REG_TRANSET, (0x00030000 | 0x17000000));
- VIA_WRITE(VIA_REG_TRANSPACE, (0x40000000 | (13 << 20) | (13 << 10) | (13)));
- VIA_WRITE(VIA_REG_TRANSPACE, (0x40000000 | (26 << 20) | (26 << 10) | (26)));
- VIA_WRITE(VIA_REG_TRANSPACE, (0x40000000 | (39 << 20) | (39 << 10) | (39)));
- VIA_WRITE(VIA_REG_TRANSPACE, ((51 << 20) | (51 << 10) | (51)));
- VIA_WRITE(VIA_REG_TRANSPACE, ((71 << 20) | (71 << 10) | (71)));
- VIA_WRITE(VIA_REG_TRANSPACE, (87 << 20) | (87 << 10) | (87));
- VIA_WRITE(VIA_REG_TRANSPACE, (113 << 20) | (113 << 10) | (113));
- VIA_WRITE(VIA_REG_TRANSPACE, (135 << 20) | (135 << 10) | (135));
- VIA_WRITE(VIA_REG_TRANSPACE, (170 << 20) | (170 << 10) | (170));
- VIA_WRITE(VIA_REG_TRANSPACE, (199 << 20) | (199 << 10) | (199));
- VIA_WRITE(VIA_REG_TRANSPACE, (246 << 20) | (246 << 10) | (246));
- VIA_WRITE(VIA_REG_TRANSPACE, (284 << 20) | (284 << 10) | (284));
- VIA_WRITE(VIA_REG_TRANSPACE, (317 << 20) | (317 << 10) | (317));
- VIA_WRITE(VIA_REG_TRANSPACE, (347 << 20) | (347 << 10) | (347));
- VIA_WRITE(VIA_REG_TRANSPACE, (373 << 20) | (373 << 10) | (373));
- VIA_WRITE(VIA_REG_TRANSPACE, (398 << 20) | (398 << 10) | (398));
- VIA_WRITE(VIA_REG_TRANSPACE, (442 << 20) | (442 << 10) | (442));
- VIA_WRITE(VIA_REG_TRANSPACE, (481 << 20) | (481 << 10) | (481));
- VIA_WRITE(VIA_REG_TRANSPACE, (517 << 20) | (517 << 10) | (517));
- VIA_WRITE(VIA_REG_TRANSPACE, (550 << 20) | (550 << 10) | (550));
- VIA_WRITE(VIA_REG_TRANSPACE, (609 << 20) | (609 << 10) | (609));
- VIA_WRITE(VIA_REG_TRANSPACE, (662 << 20) | (662 << 10) | (662));
- VIA_WRITE(VIA_REG_TRANSPACE, (709 << 20) | (709 << 10) | (709));
- VIA_WRITE(VIA_REG_TRANSPACE, (753 << 20) | (753 << 10) | (753));
- VIA_WRITE(VIA_REG_TRANSPACE, (794 << 20) | (794 << 10) | (794));
- VIA_WRITE(VIA_REG_TRANSPACE, (832 << 20) | (832 << 10) | (832));
- VIA_WRITE(VIA_REG_TRANSPACE, (868 << 20) | (868 << 10) | (868));
- VIA_WRITE(VIA_REG_TRANSPACE, (902 << 20) | (902 << 10) | (902));
- VIA_WRITE(VIA_REG_TRANSPACE, (934 << 20) | (934 << 10) | (934));
- VIA_WRITE(VIA_REG_TRANSPACE, (966 << 20) | (966 << 10) | (966));
- VIA_WRITE(VIA_REG_TRANSPACE, (996 << 20) | (996 << 10) | (996));
-
- /* Initialize INV_ParaSubType_TexPa */
- VIA_WRITE(VIA_REG_TRANSET, (0x00030000 | 0x00000000));
- for (i = 0; i < 16; i++)
- VIA_WRITE(VIA_REG_TRANSPACE, 0x00000000);
-
- /* Initialize INV_ParaSubType_4X4Cof */
- VIA_WRITE(VIA_REG_TRANSET, (0x00030000 | 0x11000000));
- for (i = 0; i < 32; i++)
- VIA_WRITE(VIA_REG_TRANSPACE, 0x00000000);
-
- /* Initialize INV_ParaSubType_StipPal */
- VIA_WRITE(VIA_REG_TRANSET, (0x00030000 | 0x14000000));
- for (i = 0; i < (5 + 3); i++)
- VIA_WRITE(VIA_REG_TRANSPACE, 0x00000000);
-
- /* primitive setting & vertex format */
- VIA_WRITE(VIA_REG_TRANSET, (0x00040000));
- for (i = 0; i <= 0x62; i++)
- VIA_WRITE(VIA_REG_TRANSPACE, (i << 24));
-
- /* c2s clamping value for screen coordinate */
- VIA_WRITE(VIA_REG_TRANSPACE, (0x50 << 24) | 0x00000000);
- VIA_WRITE(VIA_REG_TRANSPACE, (0x51 << 24) | 0x00000000);
- VIA_WRITE(VIA_REG_TRANSPACE, (0x52 << 24) | 0x00147fff);
-
- /* ParaType 0xFE - Configure and Misc Setting */
- VIA_WRITE(VIA_REG_TRANSET, (0x00fe0000));
- for (i = 0; i <= 0x47; i++)
- VIA_WRITE(VIA_REG_TRANSPACE, (i << 24));
-
- /* ParaType 0x11 - Frame Buffer Auto-Swapping and Command Regulator */
- VIA_WRITE(VIA_REG_TRANSET, (0x00110000));
- for (i = 0; i <= 0x20; i++)
- VIA_WRITE(VIA_REG_TRANSPACE, (i << 24));
-
- VIA_WRITE(VIA_REG_TRANSET, 0x00fe0000);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x4000840f);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x47000404);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x44000000);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x46000005);
-
- /* setting Misconfig */
- VIA_WRITE(VIA_REG_TRANSET, 0x00fe0000);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x00001004);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x08000249);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x0a0002c9);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x0b0002fb);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x0c000000);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x0d0002cb);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x0e000009);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x10000049);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x110002ff);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x12000008);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x130002db);
-}
-
-static void via_init_vq(struct openchrome_drm_private *dev_private)
-{
- unsigned long vq_start_addr, vq_end_addr, vqlen;
- unsigned long vqstartl, vqendl, vqstart_endh;
- struct ttm_buffer_object *bo = dev_private->vq.bo;
-
- if (!bo)
- return;
-
- vq_start_addr = bo->offset;
- vq_end_addr = vq_start_addr + bo->mem.size - 1;
- vqstartl = 0x70000000 | (vq_start_addr & 0xFFFFFF);
- vqendl = 0x71000000 | (vq_end_addr & 0xFFFFFF);
- vqstart_endh = 0x72000000 | ((vq_start_addr & 0xFF000000) >> 24) |
- ((vq_end_addr & 0xFF000000) >> 16);
- vqlen = 0x73000000 | (bo->mem.size >> 3);
-
- VIA_WRITE(0x41c, 0x00100000);
- VIA_WRITE(0x420, vqstart_endh);
- VIA_WRITE(0x420, vqstartl);
- VIA_WRITE(0x420, vqendl);
- VIA_WRITE(0x420, vqlen);
- VIA_WRITE(0x420, 0x74301001);
- VIA_WRITE(0x420, 0x00000000);
-}
-
-static void via_init_pcie_gart_table(
- struct openchrome_drm_private *dev_private,
- struct pci_dev *pdev)
-{
- struct ttm_buffer_object *bo = dev_private->gart.bo;
- u8 value;
-
- if (!pci_is_pcie(pdev) || !bo)
- return;
-
- /* enable gtt write */
- svga_wseq_mask(VGABASE, 0x6C, 0x00, BIT(7));
-
- /* set the base address of gart table */
- value = (bo->offset & 0xff000) >> 12;
- vga_wseq(VGABASE, 0x6A, value);
-
- value = (bo->offset & 0xff000) >> 20;
- vga_wseq(VGABASE, 0x6B, value);
-
- value = vga_rseq(VGABASE, 0x6C);
- value |= ((bo->offset >> 28) & 0x01);
- vga_wseq(VGABASE, 0x6C, value);
-
- /* flush the gtt cache */
- svga_wseq_mask(VGABASE, 0x6F, BIT(7), BIT(7));
-
- /* disable the gtt write */
- svga_wseq_mask(VGABASE, 0x6C, BIT(7), BIT(7));
-}
-
-/* This function does:
- * 1. Command buffer allocation
- * 2. hw engine intialization:2D;3D;VQ
- * 3. Ring Buffer mechanism setup
- */
-void via_engine_init(struct drm_device *dev)
-{
- struct openchrome_drm_private *dev_private = dev->dev_private;
-
- /* initial engines */
- via_init_2d(dev_private, dev->pdev->device);
- via_init_3d(dev_private);
- via_init_vq(dev_private);
-
- /* pcie gart table setup */
- via_init_pcie_gart_table(dev_private, dev->pdev);
-}
commit 1e1e57522b398d54ea63f5abc49c8c0003f7ae38
Author: Kevin Brace <kevinbrace at gmx.com>
Date: Mon Jan 7 17:38:18 2019 -0800
drm/openchrome: Move device initialization code into openchrome_init.c
Signed-off-by: Kevin Brace <kevinbrace at gmx.com>
diff --git a/drivers/gpu/drm/openchrome/Makefile b/drivers/gpu/drm/openchrome/Makefile
index 0cccdbe7f5a4..3ed2912e75f5 100644
--- a/drivers/gpu/drm/openchrome/Makefile
+++ b/drivers/gpu/drm/openchrome/Makefile
@@ -15,6 +15,7 @@ openchrome-y := openchrome_analog.o \
openchrome_gem.o \
openchrome_hdmi.o \
openchrome_i2c.o \
+ openchrome_init.o \
openchrome_ioc32.o \
openchrome_pm.o \
openchrome_sii164.o \
diff --git a/drivers/gpu/drm/openchrome/openchrome_drv.c b/drivers/gpu/drm/openchrome/openchrome_drv.c
index 33c0eac36e16..5dad75d5e760 100644
--- a/drivers/gpu/drm/openchrome/openchrome_drv.c
+++ b/drivers/gpu/drm/openchrome/openchrome_drv.c
@@ -53,315 +53,6 @@ MODULE_DEVICE_TABLE(pci, via_pci_table);
#define SGDMA_MEMORY (256*1024)
#define VQ_MEMORY (256*1024)
-#if IS_ENABLED(CONFIG_AGP)
-
-#define VIA_AGP_MODE_MASK 0x17
-#define VIA_AGPV3_MODE 0x08
-#define VIA_AGPV3_8X_MODE 0x02
-#define VIA_AGPV3_4X_MODE 0x01
-#define VIA_AGP_4X_MODE 0x04
-#define VIA_AGP_2X_MODE 0x02
-#define VIA_AGP_1X_MODE 0x01
-#define VIA_AGP_FW_MODE 0x10
-
-static int via_detect_agp(struct drm_device *dev)
-{
- struct openchrome_drm_private *dev_private = dev->dev_private;
- struct drm_agp_info agp_info;
- struct drm_agp_mode mode;
- int ret = 0;
-
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- ret = drm_agp_acquire(dev);
- if (ret) {
- DRM_ERROR("Failed acquiring AGP device.\n");
- return ret;
- }
-
- ret = drm_agp_info(dev, &agp_info);
- if (ret) {
- DRM_ERROR("Failed detecting AGP aperture size.\n");
- goto out_err0;
- }
-
- mode.mode = agp_info.mode & ~VIA_AGP_MODE_MASK;
- if (mode.mode & VIA_AGPV3_MODE)
- mode.mode |= VIA_AGPV3_8X_MODE;
- else
- mode.mode |= VIA_AGP_4X_MODE;
-
- mode.mode |= VIA_AGP_FW_MODE;
- ret = drm_agp_enable(dev, mode);
- if (ret) {
- DRM_ERROR("Failed to enable the AGP bus.\n");
- goto out_err0;
- }
-
- ret = ttm_bo_init_mm(&dev_private->ttm.bdev, TTM_PL_TT,
- agp_info.aperture_size >> PAGE_SHIFT);
- if (!ret) {
- DRM_INFO("Detected %lu MB of AGP Aperture at "
- "physical address 0x%08lx.\n",
- agp_info.aperture_size >> 20,
- agp_info.aperture_base);
- } else {
-out_err0:
- drm_agp_release(dev);
- }
-
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
- return ret;
-}
-
-static void via_agp_engine_init(
- struct openchrome_drm_private *dev_private)
-{
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- VIA_WRITE(VIA_REG_TRANSET, 0x00100000);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x00000000);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x00333004);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x60000000);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x61000000);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x62000000);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x63000000);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x64000000);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x7D000000);
-
- VIA_WRITE(VIA_REG_TRANSET, 0xfe020000);
- VIA_WRITE(VIA_REG_TRANSPACE, 0x00000000);
-
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
-}
-#endif
-
-static int openchrome_mmio_init(
- struct openchrome_drm_private *dev_private)
-{
- struct drm_device *dev = dev_private->dev;
- int ret = 0;
-
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- /*
- * PCI BAR1 is the MMIO memory window for all
- * VIA Technologies Chrome IGPs.
- * Obtain the starting base address and size, and
- * map it to the OS for use.
- */
- dev_private->mmio_base = pci_resource_start(dev->pdev, 1);
- dev_private->mmio_size = pci_resource_len(dev->pdev, 1);
- dev_private->mmio = ioremap(dev_private->mmio_base,
- dev_private->mmio_size);
- if (!dev_private->mmio) {
- ret = -ENOMEM;
- goto exit;
- }
-
- DRM_INFO("VIA Technologies Chrome IGP MMIO Physical Address: "
- "0x%08llx\n",
- dev_private->mmio_base);
-exit:
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
- return ret;
-}
-
-static void openchrome_mmio_fini(
- struct openchrome_drm_private *dev_private)
-{
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- if (dev_private->mmio) {
- iounmap(dev_private->mmio);
- dev_private->mmio = NULL;
- }
-
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
-}
-
-static void openchrome_graphics_unlock(
- struct openchrome_drm_private *dev_private)
-{
- uint8_t temp;
-
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- /*
- * Enable VGA subsystem.
- */
- temp = vga_io_r(0x03C3);
- vga_io_w(0x03C3, temp | 0x01);
- svga_wmisc_mask(VGABASE, BIT(0), BIT(0));
-
- /*
- * Unlock VIA Technologies Chrome IGP extended
- * registers.
- */
- svga_wseq_mask(VGABASE, 0x10, BIT(0), BIT(0));
-
- /*
- * Unlock VIA Technologies Chrome IGP extended
- * graphics functionality.
- */
- svga_wseq_mask(VGABASE, 0x1a, BIT(3), BIT(3));
-
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
-}
-
-static void chip_revision_info(
- struct openchrome_drm_private *dev_private)
-{
- struct drm_device *dev = dev_private->dev;
- struct pci_bus *bus = NULL;
- u16 device_id, subsystem_vendor_id, subsystem_device_id;
- u8 tmp;
- int pci_bus;
- u8 pci_device, pci_function;
- int ret;
-
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- /*
- * VX800, VX855, and VX900 chipsets have Chrome IGP
- * connected as Bus 0, Device 1 PCI device.
- */
- if ((dev->pdev->device == PCI_DEVICE_ID_VIA_VT1122) ||
- (dev->pdev->device == PCI_DEVICE_ID_VIA_VX875) ||
- (dev->pdev->device == PCI_DEVICE_ID_VIA_VX900_VGA)) {
-
- pci_bus = 0;
- pci_device = 1;
- pci_function = 0;
-
- /*
- * For all other devices, Chrome IGP is connected as
- * Bus 1, Device 0 PCI Device.
- */
- } else {
- pci_bus = 1;
- pci_device = 0;
- pci_function = 0;
- }
-
- bus = pci_find_bus(0, pci_bus);
- if (!bus) {
- goto pci_error;
- }
-
- ret = pci_bus_read_config_word(bus, PCI_DEVFN(pci_device,
- pci_function),
- PCI_DEVICE_ID,
- &device_id);
- if (ret) {
- goto pci_error;
- }
-
- ret = pci_bus_read_config_word(bus, PCI_DEVFN(pci_device,
- pci_function),
- PCI_SUBSYSTEM_VENDOR_ID,
- &subsystem_vendor_id);
- if (ret) {
- goto pci_error;
- }
-
- ret = pci_bus_read_config_word(bus, PCI_DEVFN(pci_device,
- pci_function),
- PCI_SUBSYSTEM_ID,
- &subsystem_device_id);
- if (ret) {
- goto pci_error;
- }
-
- DRM_DEBUG_KMS("DRM Device ID: "
- "0x%04x\n", dev->pdev->device);
- DRM_DEBUG_KMS("Chrome IGP Device ID: "
- "0x%04x\n", device_id);
- DRM_DEBUG_KMS("Chrome IGP Subsystem Vendor ID: "
- "0x%04x\n", subsystem_vendor_id);
- DRM_DEBUG_KMS("Chrome IGP Subsystem Device ID: "
- "0x%04x\n", subsystem_device_id);
-
- switch (dev->pdev->device) {
- /* CLE266 Chipset */
- case PCI_DEVICE_ID_VIA_CLE266:
- /* CR4F only defined in CLE266.CX chipset. */
- tmp = vga_rcrt(VGABASE, 0x4F);
- vga_wcrt(VGABASE, 0x4F, 0x55);
- if (vga_rcrt(VGABASE, 0x4F) != 0x55) {
- dev_private->revision = CLE266_REVISION_AX;
- } else {
- dev_private->revision = CLE266_REVISION_CX;
- }
-
- /* Restore original CR4F value. */
- vga_wcrt(VGABASE, 0x4F, tmp);
- break;
- /* CX700 / VX700 Chipset */
- case PCI_DEVICE_ID_VIA_VT3157:
- tmp = vga_rseq(VGABASE, 0x43);
- if (tmp & 0x02) {
- dev_private->revision = CX700_REVISION_700M2;
- } else if (tmp & 0x40) {
- dev_private->revision = CX700_REVISION_700M;
- } else {
- dev_private->revision = CX700_REVISION_700;
- }
-
- /* Check for VIA Technologies NanoBook reference
- * design. This is necessary due to its strapping
- * resistors not being set to indicate the
- * availability of DVI. */
- if ((subsystem_vendor_id == 0x1509) &&
- (subsystem_device_id == 0x2d30)) {
- dev_private->is_via_nanobook = true;
- } else {
- dev_private->is_via_nanobook = false;
- }
-
- break;
- /* VX800 / VX820 Chipset */
- case PCI_DEVICE_ID_VIA_VT1122:
-
- /* Check for Quanta IL1 netbook. This is necessary
- * due to its flat panel connected to DVP1 (Digital
- * Video Port 1) rather than its LVDS channel. */
- if ((subsystem_vendor_id == 0x152d) &&
- (subsystem_device_id == 0x0771)) {
- dev_private->is_quanta_il1 = true;
- } else {
- dev_private->is_quanta_il1 = false;
- }
-
- /* Samsung NC20 netbook has its FP connected to LVDS2
- * rather than the more logical LVDS1, hence, a special
- * flag register is needed for properly controlling its
- * FP. */
- if ((subsystem_vendor_id == 0x144d) &&
- (subsystem_device_id == 0xc04e)) {
- dev_private->is_samsung_nc20 = true;
- } else {
- dev_private->is_samsung_nc20 = false;
- }
-
- break;
- /* VX855 / VX875 Chipset */
- case PCI_DEVICE_ID_VIA_VX875:
- /* VX900 Chipset */
- case PCI_DEVICE_ID_VIA_VX900_VGA:
- dev_private->revision = vga_rseq(VGABASE, 0x3B);
- break;
- default:
- break;
- }
-
- goto exit;
-pci_error:
- DRM_ERROR("PCI bus related error.");
-exit:
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
-}
-
static int via_dumb_create(struct drm_file *filp,
struct drm_device *dev,
struct drm_mode_create_dumb *args)
@@ -425,55 +116,6 @@ static int gem_dumb_destroy(struct drm_file *filp,
return ret;
}
-static void openchrome_flag_init(
- struct openchrome_drm_private *dev_private)
-{
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- /*
- * Special handling flags for a few special models.
- */
- dev_private->is_via_nanobook = false;
- dev_private->is_quanta_il1 = false;
-
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
-}
-
-static int via_device_init(struct openchrome_drm_private *dev_private)
-{
- int ret;
-
- DRM_DEBUG_KMS("Entered %s.\n", __func__);
-
- openchrome_flag_init(dev_private);
-
- ret = via_vram_detect(dev_private);
- if (ret) {
- DRM_ERROR("Failed to detect video RAM.\n");
- goto exit;
- }
-
- /*
- * Map VRAM.
- */
- ret = openchrome_vram_init(dev_private);
- if (ret) {
- DRM_ERROR("Failed to initialize video RAM.\n");
- goto exit;
- }
-
- ret = openchrome_mmio_init(dev_private);
- if (ret) {
- DRM_ERROR("Failed to initialize MMIO.\n");
- goto exit;
- }
-
- openchrome_graphics_unlock(dev_private);
-exit:
- DRM_DEBUG_KMS("Exiting %s.\n", __func__);
- return ret;
-}
-
static void via_driver_unload(struct drm_device *dev)
{
struct openchrome_drm_private *dev_private = dev->dev_private;
@@ -540,7 +182,7 @@ static int via_driver_load(struct drm_device *dev,
dev_private->vram_mtrr = -ENXIO;
dev_private->dev = dev;
- ret = via_device_init(dev_private);
+ ret = openchrome_device_init(dev_private);
if (ret) {
DRM_ERROR("Failed to initialize Chrome IGP.\n");
goto init_error;
diff --git a/drivers/gpu/drm/openchrome/openchrome_drv.h b/drivers/gpu/drm/openchrome/openchrome_drv.h
index 494eb439df74..6a16169c4e85 100644
--- a/drivers/gpu/drm/openchrome/openchrome_drv.h
+++ b/drivers/gpu/drm/openchrome/openchrome_drv.h
@@ -263,6 +263,18 @@ extern int via_max_ioctl;
extern int via_hdmi_audio;
+#if IS_ENABLED(CONFIG_AGP)
+int via_detect_agp(struct drm_device *dev);
+void via_agp_engine_init(struct openchrome_drm_private *dev_private);
+#endif /* IS_ENABLED(CONFIG_AGP) */
+int openchrome_mmio_init(struct openchrome_drm_private *dev_private);
+void openchrome_mmio_fini(struct openchrome_drm_private *dev_private);
+void openchrome_graphics_unlock(
+ struct openchrome_drm_private *dev_private);
+void chip_revision_info(struct openchrome_drm_private *dev_private);
+void openchrome_flag_init(struct openchrome_drm_private *dev_private);
+int openchrome_device_init(struct openchrome_drm_private *dev_private);
+
extern void via_engine_init(struct drm_device *dev);
extern int via_vram_detect(struct openchrome_drm_private *dev_private);
diff --git a/drivers/gpu/drm/openchrome/openchrome_init.c b/drivers/gpu/drm/openchrome/openchrome_init.c
new file mode 100644
index 000000000000..dd3807ad2f40
--- /dev/null
+++ b/drivers/gpu/drm/openchrome/openchrome_init.c
@@ -0,0 +1,386 @@
+/*
+ * Copyright 2017 Kevin Brace. All Rights Reserved.
+ * Copyright 2012 James Simmons <jsimmons at infradead.org>. All Rights Reserved.
+ * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
+ * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sub license,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include <linux/module.h>
+#include <linux/console.h>
+
+#include <drm/drmP.h>
+#include "openchrome_drv.h"
+
+
+#if IS_ENABLED(CONFIG_AGP)
+
+#define VIA_AGP_MODE_MASK 0x17
+#define VIA_AGPV3_MODE 0x08
+#define VIA_AGPV3_8X_MODE 0x02
+#define VIA_AGPV3_4X_MODE 0x01
+#define VIA_AGP_4X_MODE 0x04
+#define VIA_AGP_2X_MODE 0x02
+#define VIA_AGP_1X_MODE 0x01
+#define VIA_AGP_FW_MODE 0x10
+
+int via_detect_agp(struct drm_device *dev)
+{
+ struct openchrome_drm_private *dev_private = dev->dev_private;
+ struct drm_agp_info agp_info;
+ struct drm_agp_mode mode;
+ int ret = 0;
+
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ ret = drm_agp_acquire(dev);
+ if (ret) {
+ DRM_ERROR("Failed acquiring AGP device.\n");
+ return ret;
+ }
+
+ ret = drm_agp_info(dev, &agp_info);
+ if (ret) {
+ DRM_ERROR("Failed detecting AGP aperture size.\n");
+ goto out_err0;
+ }
+
+ mode.mode = agp_info.mode & ~VIA_AGP_MODE_MASK;
+ if (mode.mode & VIA_AGPV3_MODE)
+ mode.mode |= VIA_AGPV3_8X_MODE;
+ else
+ mode.mode |= VIA_AGP_4X_MODE;
+
+ mode.mode |= VIA_AGP_FW_MODE;
+ ret = drm_agp_enable(dev, mode);
+ if (ret) {
+ DRM_ERROR("Failed to enable the AGP bus.\n");
+ goto out_err0;
+ }
+
+ ret = ttm_bo_init_mm(&dev_private->ttm.bdev, TTM_PL_TT,
+ agp_info.aperture_size >> PAGE_SHIFT);
+ if (!ret) {
+ DRM_INFO("Detected %lu MB of AGP Aperture at "
+ "physical address 0x%08lx.\n",
+ agp_info.aperture_size >> 20,
+ agp_info.aperture_base);
+ } else {
+out_err0:
+ drm_agp_release(dev);
+ }
+
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+ return ret;
+}
+
+void via_agp_engine_init(struct openchrome_drm_private *dev_private)
+{
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ VIA_WRITE(VIA_REG_TRANSET, 0x00100000);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x00000000);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x00333004);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x60000000);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x61000000);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x62000000);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x63000000);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x64000000);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x7D000000);
+
+ VIA_WRITE(VIA_REG_TRANSET, 0xfe020000);
+ VIA_WRITE(VIA_REG_TRANSPACE, 0x00000000);
+
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+#endif
+
+int openchrome_mmio_init(
+ struct openchrome_drm_private *dev_private)
+{
+ struct drm_device *dev = dev_private->dev;
+ int ret = 0;
+
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ /*
+ * PCI BAR1 is the MMIO memory window for all
+ * VIA Technologies Chrome IGPs.
+ * Obtain the starting base address and size, and
+ * map it to the OS for use.
+ */
+ dev_private->mmio_base = pci_resource_start(dev->pdev, 1);
+ dev_private->mmio_size = pci_resource_len(dev->pdev, 1);
+ dev_private->mmio = ioremap(dev_private->mmio_base,
+ dev_private->mmio_size);
+ if (!dev_private->mmio) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+
+ DRM_INFO("VIA Technologies Chrome IGP MMIO Physical Address: "
+ "0x%08llx\n",
+ dev_private->mmio_base);
+exit:
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+ return ret;
+}
+
+void openchrome_mmio_fini(struct openchrome_drm_private *dev_private)
+{
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ if (dev_private->mmio) {
+ iounmap(dev_private->mmio);
+ dev_private->mmio = NULL;
+ }
+
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+void openchrome_graphics_unlock(
+ struct openchrome_drm_private *dev_private)
+{
+ uint8_t temp;
+
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ /*
+ * Enable VGA subsystem.
+ */
+ temp = vga_io_r(0x03C3);
+ vga_io_w(0x03C3, temp | 0x01);
+ svga_wmisc_mask(VGABASE, BIT(0), BIT(0));
+
+ /*
+ * Unlock VIA Technologies Chrome IGP extended
+ * registers.
+ */
+ svga_wseq_mask(VGABASE, 0x10, BIT(0), BIT(0));
+
+ /*
+ * Unlock VIA Technologies Chrome IGP extended
+ * graphics functionality.
+ */
+ svga_wseq_mask(VGABASE, 0x1a, BIT(3), BIT(3));
+
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+void chip_revision_info(struct openchrome_drm_private *dev_private)
+{
+ struct drm_device *dev = dev_private->dev;
+ struct pci_bus *bus = NULL;
+ u16 device_id, subsystem_vendor_id, subsystem_device_id;
+ u8 tmp;
+ int pci_bus;
+ u8 pci_device, pci_function;
+ int ret;
+
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ /*
+ * VX800, VX855, and VX900 chipsets have Chrome IGP
+ * connected as Bus 0, Device 1 PCI device.
+ */
+ if ((dev->pdev->device == PCI_DEVICE_ID_VIA_VT1122) ||
+ (dev->pdev->device == PCI_DEVICE_ID_VIA_VX875) ||
+ (dev->pdev->device == PCI_DEVICE_ID_VIA_VX900_VGA)) {
+
+ pci_bus = 0;
+ pci_device = 1;
+ pci_function = 0;
+
+ /*
+ * For all other devices, Chrome IGP is connected as
+ * Bus 1, Device 0 PCI Device.
+ */
+ } else {
+ pci_bus = 1;
+ pci_device = 0;
+ pci_function = 0;
+ }
+
+ bus = pci_find_bus(0, pci_bus);
+ if (!bus) {
+ goto pci_error;
+ }
+
+ ret = pci_bus_read_config_word(bus, PCI_DEVFN(pci_device,
+ pci_function),
+ PCI_DEVICE_ID,
+ &device_id);
+ if (ret) {
+ goto pci_error;
+ }
+
+ ret = pci_bus_read_config_word(bus, PCI_DEVFN(pci_device,
+ pci_function),
+ PCI_SUBSYSTEM_VENDOR_ID,
+ &subsystem_vendor_id);
+ if (ret) {
+ goto pci_error;
+ }
+
+ ret = pci_bus_read_config_word(bus, PCI_DEVFN(pci_device,
+ pci_function),
+ PCI_SUBSYSTEM_ID,
+ &subsystem_device_id);
+ if (ret) {
+ goto pci_error;
+ }
+
+ DRM_DEBUG_KMS("DRM Device ID: "
+ "0x%04x\n", dev->pdev->device);
+ DRM_DEBUG_KMS("Chrome IGP Device ID: "
+ "0x%04x\n", device_id);
+ DRM_DEBUG_KMS("Chrome IGP Subsystem Vendor ID: "
+ "0x%04x\n", subsystem_vendor_id);
+ DRM_DEBUG_KMS("Chrome IGP Subsystem Device ID: "
+ "0x%04x\n", subsystem_device_id);
+
+ switch (dev->pdev->device) {
+ /* CLE266 Chipset */
+ case PCI_DEVICE_ID_VIA_CLE266:
+ /* CR4F only defined in CLE266.CX chipset. */
+ tmp = vga_rcrt(VGABASE, 0x4F);
+ vga_wcrt(VGABASE, 0x4F, 0x55);
+ if (vga_rcrt(VGABASE, 0x4F) != 0x55) {
+ dev_private->revision = CLE266_REVISION_AX;
+ } else {
+ dev_private->revision = CLE266_REVISION_CX;
+ }
+
+ /* Restore original CR4F value. */
+ vga_wcrt(VGABASE, 0x4F, tmp);
+ break;
+ /* CX700 / VX700 Chipset */
+ case PCI_DEVICE_ID_VIA_VT3157:
+ tmp = vga_rseq(VGABASE, 0x43);
+ if (tmp & 0x02) {
+ dev_private->revision = CX700_REVISION_700M2;
+ } else if (tmp & 0x40) {
+ dev_private->revision = CX700_REVISION_700M;
+ } else {
+ dev_private->revision = CX700_REVISION_700;
+ }
+
+ /* Check for VIA Technologies NanoBook reference
+ * design. This is necessary due to its strapping
+ * resistors not being set to indicate the
+ * availability of DVI. */
+ if ((subsystem_vendor_id == 0x1509) &&
+ (subsystem_device_id == 0x2d30)) {
+ dev_private->is_via_nanobook = true;
+ } else {
+ dev_private->is_via_nanobook = false;
+ }
+
+ break;
+ /* VX800 / VX820 Chipset */
+ case PCI_DEVICE_ID_VIA_VT1122:
+
+ /* Check for Quanta IL1 netbook. This is necessary
+ * due to its flat panel connected to DVP1 (Digital
+ * Video Port 1) rather than its LVDS channel. */
+ if ((subsystem_vendor_id == 0x152d) &&
+ (subsystem_device_id == 0x0771)) {
+ dev_private->is_quanta_il1 = true;
+ } else {
+ dev_private->is_quanta_il1 = false;
+ }
+
+ /* Samsung NC20 netbook has its FP connected to LVDS2
+ * rather than the more logical LVDS1, hence, a special
+ * flag register is needed for properly controlling its
+ * FP. */
+ if ((subsystem_vendor_id == 0x144d) &&
+ (subsystem_device_id == 0xc04e)) {
+ dev_private->is_samsung_nc20 = true;
+ } else {
+ dev_private->is_samsung_nc20 = false;
+ }
+
+ break;
+ /* VX855 / VX875 Chipset */
+ case PCI_DEVICE_ID_VIA_VX875:
+ /* VX900 Chipset */
+ case PCI_DEVICE_ID_VIA_VX900_VGA:
+ dev_private->revision = vga_rseq(VGABASE, 0x3B);
+ break;
+ default:
+ break;
+ }
+
+ goto exit;
+pci_error:
+ DRM_ERROR("PCI bus related error.");
+exit:
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+void openchrome_flag_init(struct openchrome_drm_private *dev_private)
+{
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ /*
+ * Special handling flags for a few special models.
+ */
+ dev_private->is_via_nanobook = false;
+ dev_private->is_quanta_il1 = false;
+
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
+int openchrome_device_init(struct openchrome_drm_private *dev_private)
+{
+ int ret;
+
+ DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+ openchrome_flag_init(dev_private);
+
+ ret = via_vram_detect(dev_private);
+ if (ret) {
+ DRM_ERROR("Failed to detect video RAM.\n");
+ goto exit;
+ }
+
+ /*
+ * Map VRAM.
+ */
+ ret = openchrome_vram_init(dev_private);
+ if (ret) {
+ DRM_ERROR("Failed to initialize video RAM.\n");
+ goto exit;
+ }
+
+ ret = openchrome_mmio_init(dev_private);
+ if (ret) {
+ DRM_ERROR("Failed to initialize MMIO.\n");
+ goto exit;
+ }
+
+ openchrome_graphics_unlock(dev_private);
+exit:
+ DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+ return ret;
+}
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