[openchrome-devel] drm-openchrome: Branch 'drm-next-5.20' - 9 commits - drivers/gpu/drm

Kevin Brace kevinbrace at kemper.freedesktop.org
Tue Jul 5 22:24:49 UTC 2022


 drivers/gpu/drm/via/via_crtc.c    |   15 +++-
 drivers/gpu/drm/via/via_crtc_hw.h |  142 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/via/via_drv.h     |    8 +-
 drivers/gpu/drm/via/via_encoder.c |   52 +++++++++++++
 drivers/gpu/drm/via/via_lvds.c    |    7 +
 drivers/gpu/drm/via/via_sii164.c  |   15 ++++
 drivers/gpu/drm/via/via_tmds.c    |   18 ++--
 drivers/gpu/drm/via/via_vt1632.c  |   15 ++++
 8 files changed, 256 insertions(+), 16 deletions(-)

New commits:
commit 61d1eeac0d426b2b8ce30aecf84b8532d4d55813
Author: Kevin Brace <kevinbrace at bracecomputerlab.com>
Date:   Tue Jul 5 17:13:17 2022 -0500

    drm/via: Version bumped to 3.5.4
    
    Added the necessary enablement code to support Silicon Image SiI 164
    and VIA Technologies VT1632(A) DVI transmitter on CLE266 chipset.  Now
    the KMS mode setting code should be display device support feature
    parity with the legacy UMS mode setting code.
    
    Signed-off-by: Kevin Brace <kevinbrace at bracecomputerlab.com>

diff --git a/drivers/gpu/drm/via/via_drv.h b/drivers/gpu/drm/via/via_drv.h
index 1da0a191f9a8..5b4a1b0b8234 100644
--- a/drivers/gpu/drm/via/via_drv.h
+++ b/drivers/gpu/drm/via/via_drv.h
@@ -50,10 +50,10 @@
 
 #define DRIVER_MAJOR		3
 #define DRIVER_MINOR		5
-#define DRIVER_PATCHLEVEL	3
+#define DRIVER_PATCHLEVEL	4
 #define DRIVER_NAME		"via"
 #define DRIVER_DESC		"OpenChrome DRM for VIA Technologies Chrome IGP"
-#define DRIVER_DATE		"20220701"
+#define DRIVER_DATE		"20220705"
 #define DRIVER_AUTHOR		"OpenChrome Project"
 
 
commit a2d2af13895e861194fead01bbee9b8637578a0d
Author: Kevin Brace <kevinbrace at bracecomputerlab.com>
Date:   Tue Jul 5 16:59:03 2022 -0500

    drm/via: Add via_clock_source() to specify DIPx clock source
    
    Borrowed from OpenChrome DDX commit 7b385b3.
    
    Signed-off-by: Kevin Brace <kevinbrace at bracecomputerlab.com>

diff --git a/drivers/gpu/drm/via/via_crtc_hw.h b/drivers/gpu/drm/via/via_crtc_hw.h
index 7fc75d574ba7..4a6b785324bd 100644
--- a/drivers/gpu/drm/via/via_crtc_hw.h
+++ b/drivers/gpu/drm/via/via_crtc_hw.h
@@ -188,6 +188,23 @@ via_dip0_set_output_enable(void __iomem *regs, bool output_enable)
 			output_enable ? "Enable" : "Disable");
 }
 
+/*
+ * Sets the clock source of DIP0 (Digital Interface Port 0)
+ * interface. CLE266 chipset only.
+ */
+static inline void
+via_dip0_set_clock_source(void __iomem *regs, bool clock_source)
+{
+	/*
+	 * 3X5.6C[5] - DIP0 Clock Source
+	 *             0: External
+	 *             1: Internal
+	 */
+	svga_wcrt_mask(regs, 0x6c, clock_source ? BIT(5) : 0x00, BIT(5));
+	DRM_DEBUG_KMS("DIP0 Clock Source: %s\n",
+			clock_source ? "Internal" : "External");
+}
+
 /*
  * Sets the display source of DIP0 (Digital Interface Port 0) interface.
  * CLE266 chipset only.
@@ -242,6 +259,23 @@ via_dip1_set_output_enable(void __iomem *regs, bool output_enable)
 			output_enable ? "Enable" : "Disable");
 }
 
+/*
+ * Sets the clock source of DIP1 (Digital Interface Port 1)
+ * interface. CLE266 chipset only.
+ */
+static inline void
+via_dip1_set_clock_source(void __iomem *regs, bool clock_source)
+{
+	/*
+	 * 3X5.93[5] - DIP1 Clock Source
+	 *             0: External
+	 *             1: Internal
+	 */
+	svga_wcrt_mask(regs, 0x93, clock_source ? BIT(5) : 0x00, BIT(5));
+	DRM_DEBUG_KMS("DIP1 Clock Source: %s\n",
+			clock_source ? "Internal" : "External");
+}
+
 /*
  * Sets the display source of DIP1 (Digital Interface Port 1)
  * interface. CLE266 chipset only.
diff --git a/drivers/gpu/drm/via/via_drv.h b/drivers/gpu/drm/via/via_drv.h
index 878694da9ce5..1da0a191f9a8 100644
--- a/drivers/gpu/drm/via/via_drv.h
+++ b/drivers/gpu/drm/via/via_drv.h
@@ -363,6 +363,8 @@ void via_transmitter_io_pad_state(struct via_drm_priv *dev_priv,
 					uint32_t di_port, bool io_pad_on);
 void via_output_enable(struct via_drm_priv *dev_priv,
 			uint32_t di_port, bool output_enable);
+void via_clock_source(struct via_drm_priv *dev_priv, uint32_t di_port,
+			bool clock_source);
 void via_transmitter_clock_drive_strength(struct via_drm_priv *dev_priv,
 					u32 di_port, u8 drive_strength);
 void via_transmitter_data_drive_strength(struct via_drm_priv *dev_priv,
diff --git a/drivers/gpu/drm/via/via_encoder.c b/drivers/gpu/drm/via/via_encoder.c
index b6db65ec8797..43c47e53b43e 100644
--- a/drivers/gpu/drm/via/via_encoder.c
+++ b/drivers/gpu/drm/via/via_encoder.c
@@ -109,6 +109,25 @@ void via_output_enable(struct via_drm_priv *dev_priv, uint32_t di_port,
 	DRM_DEBUG_KMS("Exiting %s.\n", __func__);
 }
 
+void via_clock_source(struct via_drm_priv *dev_priv, uint32_t di_port,
+			bool clock_source)
+{
+	DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+	switch(di_port) {
+	case VIA_DI_PORT_DIP0:
+		via_dip0_set_clock_source(VGABASE, clock_source);
+		break;
+	case VIA_DI_PORT_DIP1:
+		via_dip1_set_clock_source(VGABASE, clock_source);
+		break;
+	default:
+		break;
+	}
+
+	DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
 void via_transmitter_clock_drive_strength(
 					struct via_drm_priv *dev_priv,
 					u32 di_port, u8 drive_strength)
diff --git a/drivers/gpu/drm/via/via_sii164.c b/drivers/gpu/drm/via/via_sii164.c
index 14b7e54c6d8d..05a4c0230fd7 100644
--- a/drivers/gpu/drm/via/via_sii164.c
+++ b/drivers/gpu/drm/via/via_sii164.c
@@ -192,6 +192,7 @@ static void via_sii164_mode_set(struct drm_encoder *encoder,
 	struct via_encoder *enc = container_of(encoder,
 					struct via_encoder, base);
 	struct drm_device *dev = encoder->dev;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
 	struct i2c_adapter *i2c_bus;
 
@@ -215,6 +216,9 @@ static void via_sii164_mode_set(struct drm_encoder *encoder,
 	via_transmitter_clock_drive_strength(dev_priv, enc->di_port, 0x03);
 	via_transmitter_data_drive_strength(dev_priv, enc->di_port, 0x03);
 	via_transmitter_io_pad_state(dev_priv, enc->di_port, true);
+	if (pdev->device == PCI_DEVICE_ID_VIA_CLE266_GFX) {
+		via_clock_source(dev_priv, enc->di_port, true);
+	}
 
 	via_sii164_display_registers(i2c_bus);
 	via_sii164_init_registers(i2c_bus);
diff --git a/drivers/gpu/drm/via/via_vt1632.c b/drivers/gpu/drm/via/via_vt1632.c
index a71c8632936e..30e004e421c0 100644
--- a/drivers/gpu/drm/via/via_vt1632.c
+++ b/drivers/gpu/drm/via/via_vt1632.c
@@ -212,6 +212,7 @@ static void via_vt1632_mode_set(struct drm_encoder *encoder,
 	struct via_encoder *enc = container_of(encoder,
 					struct via_encoder, base);
 	struct drm_device *dev = encoder->dev;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
 	struct i2c_adapter *i2c_bus;
 
@@ -235,6 +236,9 @@ static void via_vt1632_mode_set(struct drm_encoder *encoder,
 	via_transmitter_clock_drive_strength(dev_priv, enc->di_port, 0x03);
 	via_transmitter_data_drive_strength(dev_priv, enc->di_port, 0x03);
 	via_transmitter_io_pad_state(dev_priv, enc->di_port, true);
+	if (pdev->device == PCI_DEVICE_ID_VIA_CLE266_GFX) {
+		via_clock_source(dev_priv, enc->di_port, true);
+	}
 
 	via_vt1632_display_registers(i2c_bus);
 	via_vt1632_init_registers(i2c_bus);
commit 19cd349ef15ecc89fe67808adb4b83b7be7fbc53
Author: Kevin Brace <kevinbrace at bracecomputerlab.com>
Date:   Tue Jul 5 16:56:13 2022 -0500

    drm/via: Add via_output_enable() to control DIPx output status
    
    Borrowed from OpenChrome DDX commit 50b5b95.
    
    Signed-off-by: Kevin Brace <kevinbrace at bracecomputerlab.com>

diff --git a/drivers/gpu/drm/via/via_crtc_hw.h b/drivers/gpu/drm/via/via_crtc_hw.h
index d8f22114c4f6..7fc75d574ba7 100644
--- a/drivers/gpu/drm/via/via_crtc_hw.h
+++ b/drivers/gpu/drm/via/via_crtc_hw.h
@@ -171,6 +171,23 @@ via_dip0_set_io_pad_state(void __iomem *regs, u8 io_pad_state)
 								       "Off");
 }
 
+/*
+ * Output enable of DIP0 (Digital Interface Port 0) interface.
+ * CLE266 chipset only.
+ */
+static inline void
+via_dip0_set_output_enable(void __iomem *regs, bool output_enable)
+{
+	/*
+	* 3X5.6C[0] - DIP0 Output Enable
+	*             0: Output Disable
+	*             1: Output Enable
+	*/
+	svga_wcrt_mask(regs, 0x6c, output_enable ? BIT(0) : 0x00, BIT(0));
+	DRM_DEBUG_KMS("DIP0 Output: %s\n",
+			output_enable ? "Enable" : "Disable");
+}
+
 /*
  * Sets the display source of DIP0 (Digital Interface Port 0) interface.
  * CLE266 chipset only.
@@ -208,6 +225,23 @@ via_dip1_set_io_pad_state(void __iomem *regs, u8 io_pad_state)
 									"Off");
 }
 
+/*
+ * Output enable of DIP1 (Digital Interface Port 1) interface.
+ * CLE266 chipset only.
+ */
+static inline void
+via_dip1_set_output_enable(void __iomem *regs, bool output_enable)
+{
+	/*
+	 * 3X5.93[0] - DIP1 Output Enable
+	 *             0: Output Disable
+	 *             1: Output Enable
+	 */
+	svga_wcrt_mask(regs, 0x93, output_enable ? BIT(0) : 0x00, BIT(0));
+	DRM_DEBUG_KMS("DIP1 Output: %s\n",
+			output_enable ? "Enable" : "Disable");
+}
+
 /*
  * Sets the display source of DIP1 (Digital Interface Port 1)
  * interface. CLE266 chipset only.
diff --git a/drivers/gpu/drm/via/via_drv.h b/drivers/gpu/drm/via/via_drv.h
index 1c801d525a24..878694da9ce5 100644
--- a/drivers/gpu/drm/via/via_drv.h
+++ b/drivers/gpu/drm/via/via_drv.h
@@ -361,6 +361,8 @@ void via_mm_fini(struct via_drm_priv *dev_priv);
 
 void via_transmitter_io_pad_state(struct via_drm_priv *dev_priv,
 					uint32_t di_port, bool io_pad_on);
+void via_output_enable(struct via_drm_priv *dev_priv,
+			uint32_t di_port, bool output_enable);
 void via_transmitter_clock_drive_strength(struct via_drm_priv *dev_priv,
 					u32 di_port, u8 drive_strength);
 void via_transmitter_data_drive_strength(struct via_drm_priv *dev_priv,
diff --git a/drivers/gpu/drm/via/via_encoder.c b/drivers/gpu/drm/via/via_encoder.c
index fd01176d07e4..b6db65ec8797 100644
--- a/drivers/gpu/drm/via/via_encoder.c
+++ b/drivers/gpu/drm/via/via_encoder.c
@@ -90,6 +90,25 @@ void via_transmitter_io_pad_state(struct via_drm_priv *dev_priv,
 	DRM_DEBUG_KMS("Exiting %s.\n", __func__);
 }
 
+void via_output_enable(struct via_drm_priv *dev_priv, uint32_t di_port,
+			bool output_enable)
+{
+	DRM_DEBUG_KMS("Entered %s.\n", __func__);
+
+	switch(di_port) {
+	case VIA_DI_PORT_DIP0:
+		via_dip0_set_output_enable(VGABASE, output_enable);
+		break;
+	case VIA_DI_PORT_DIP1:
+		via_dip1_set_output_enable(VGABASE, output_enable);
+		break;
+	default:
+		break;
+	}
+
+	DRM_DEBUG_KMS("Exiting %s.\n", __func__);
+}
+
 void via_transmitter_clock_drive_strength(
 					struct via_drm_priv *dev_priv,
 					u32 di_port, u8 drive_strength)
diff --git a/drivers/gpu/drm/via/via_sii164.c b/drivers/gpu/drm/via/via_sii164.c
index 76f8dd783eca..14b7e54c6d8d 100644
--- a/drivers/gpu/drm/via/via_sii164.c
+++ b/drivers/gpu/drm/via/via_sii164.c
@@ -24,6 +24,8 @@
  * Kevin Brace <kevinbrace at bracecomputerlab.com>
  */
 
+#include <linux/pci.h>
+
 #include <drm/drm_atomic_state_helper.h>
 #include <drm/drm_probe_helper.h>
 
@@ -229,6 +231,7 @@ static void via_sii164_prepare(struct drm_encoder *encoder)
 	struct via_encoder *enc = container_of(encoder,
 					struct via_encoder, base);
 	struct drm_device *dev = encoder->dev;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
 	struct i2c_adapter *i2c_bus;
 
@@ -251,6 +254,10 @@ static void via_sii164_prepare(struct drm_encoder *encoder)
 
 	via_sii164_power(i2c_bus, false);
 	via_transmitter_io_pad_state(dev_priv, enc->di_port, false);
+	if (pdev->device == PCI_DEVICE_ID_VIA_CLE266_GFX) {
+		via_output_enable(dev_priv, enc->di_port, false);
+	}
+
 exit:
 	DRM_DEBUG_KMS("Exiting %s.\n", __func__);
 }
@@ -260,6 +267,7 @@ static void via_sii164_commit(struct drm_encoder *encoder)
 	struct via_encoder *enc = container_of(encoder,
 					struct via_encoder, base);
 	struct drm_device *dev = encoder->dev;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
 	struct i2c_adapter *i2c_bus;
 
@@ -282,6 +290,9 @@ static void via_sii164_commit(struct drm_encoder *encoder)
 
 	via_sii164_power(i2c_bus, true);
 	via_transmitter_io_pad_state(dev_priv, enc->di_port, true);
+	if (pdev->device == PCI_DEVICE_ID_VIA_CLE266_GFX) {
+		via_output_enable(dev_priv, enc->di_port, true);
+	}
 
 exit:
 	DRM_DEBUG_KMS("Exiting %s.\n", __func__);
diff --git a/drivers/gpu/drm/via/via_vt1632.c b/drivers/gpu/drm/via/via_vt1632.c
index c621b116933b..a71c8632936e 100644
--- a/drivers/gpu/drm/via/via_vt1632.c
+++ b/drivers/gpu/drm/via/via_vt1632.c
@@ -24,6 +24,8 @@
  * Kevin Brace <kevinbrace at bracecomputerlab.com>
  */
 
+#include <linux/pci.h>
+
 #include <drm/drm_atomic_state_helper.h>
 #include <drm/drm_probe_helper.h>
 
@@ -249,6 +251,7 @@ static void via_vt1632_prepare(struct drm_encoder *encoder)
 	struct via_encoder *enc = container_of(encoder,
 					struct via_encoder, base);
 	struct drm_device *dev = encoder->dev;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
 	struct i2c_adapter *i2c_bus;
 
@@ -271,6 +274,10 @@ static void via_vt1632_prepare(struct drm_encoder *encoder)
 
 	via_vt1632_power(i2c_bus, false);
 	via_transmitter_io_pad_state(dev_priv, enc->di_port, false);
+	if (pdev->device == PCI_DEVICE_ID_VIA_CLE266_GFX) {
+		via_output_enable(dev_priv, enc->di_port, false);
+	}
+
 exit:
 	DRM_DEBUG_KMS("Exiting %s.\n", __func__);
 }
@@ -280,6 +287,7 @@ static void via_vt1632_commit(struct drm_encoder *encoder)
 	struct via_encoder *enc = container_of(encoder,
 					struct via_encoder, base);
 	struct drm_device *dev = encoder->dev;
+	struct pci_dev *pdev = to_pci_dev(dev->dev);
 	struct via_drm_priv *dev_priv = to_via_drm_priv(dev);
 	struct i2c_adapter *i2c_bus;
 
@@ -302,6 +310,9 @@ static void via_vt1632_commit(struct drm_encoder *encoder)
 
 	via_vt1632_power(i2c_bus, true);
 	via_transmitter_io_pad_state(dev_priv, enc->di_port, true);
+	if (pdev->device == PCI_DEVICE_ID_VIA_CLE266_GFX) {
+		via_output_enable(dev_priv, enc->di_port, true);
+	}
 
 exit:
 	DRM_DEBUG_KMS("Exiting %s.\n", __func__);
commit 895e125125fc487136676dfd4bb6cb92f38ed0ad
Author: Kevin Brace <kevinbrace at bracecomputerlab.com>
Date:   Tue Jul 5 16:56:11 2022 -0500

    drm/via: Fix for screen distortion when CLE266 chipset's IGA2 is being used
    
    Not resetting CR55[7] to 0 causes screen distortion on CLE266 chipset's
    screen driven by IGA2.  Borrowed from OpenChrome DDX commit 6784fa3.
    
    Signed-off-by: Kevin Brace <kevinbrace at bracecomputerlab.com>

diff --git a/drivers/gpu/drm/via/via_crtc.c b/drivers/gpu/drm/via/via_crtc.c
index 55224ae03ae8..d00f56d8c974 100644
--- a/drivers/gpu/drm/via/via_crtc.c
+++ b/drivers/gpu/drm/via/via_crtc.c
@@ -79,6 +79,15 @@ static void via_iga_common_init(struct pci_dev *pdev, void __iomem *regs)
 	 *               1: Enable */
 	svga_wseq_mask(regs, 0x15, BIT(5) | BIT(1), BIT(5) | BIT(1));
 
+	/*
+	 * It was observed on NeoWare CA10 thin client with DVI that not
+	 * resetting CR55[7] to 0 causes the screen driven by IGA2 to get
+	 * distorted.
+	 */
+	if (pdev->device == PCI_DEVICE_ID_VIA_CLE266_GFX) {
+		svga_wcrt_mask(regs, 0x55, 0x00, BIT(7));
+	}
+
 	/*
 	 * Disable simultaneous display.
 	 * Turning this on causes IGA1 to have a display issue.
commit 804a9fb69ff996ffc0ca16a65d3b9b214fd01145
Author: Kevin Brace <kevinbrace at bracecomputerlab.com>
Date:   Tue Jul 5 16:56:10 2022 -0500

    drm/via: Add pdev as an input parameter for via_iga_common_init()
    
    Signed-off-by: Kevin Brace <kevinbrace at bracecomputerlab.com>

diff --git a/drivers/gpu/drm/via/via_crtc.c b/drivers/gpu/drm/via/via_crtc.c
index 6203c2d53231..55224ae03ae8 100644
--- a/drivers/gpu/drm/via/via_crtc.c
+++ b/drivers/gpu/drm/via/via_crtc.c
@@ -65,7 +65,7 @@ static struct vga_regset vpit_table[] = {
 	{VGA_GFX_I, 0x08, 0xFF, 0xFF }
 };
 
-static void via_iga_common_init(void __iomem *regs)
+static void via_iga_common_init(struct pci_dev *pdev, void __iomem *regs)
 {
 	DRM_DEBUG_KMS("Entered %s.\n", __func__);
 
@@ -1657,7 +1657,7 @@ void via_mode_set_nofb(struct drm_crtc *crtc)
 			via_set_vclock(crtc, pll_regs);
 		}
 
-		via_iga_common_init(VGABASE);
+		via_iga_common_init(pdev, VGABASE);
 
 		/* Set palette LUT to 8-bit mode. */
 		via_iga1_set_palette_lut_resolution(VGABASE, true);
@@ -1776,7 +1776,7 @@ void via_mode_set_nofb(struct drm_crtc *crtc)
 			via_set_vclock(crtc, pll_regs);
 		}
 
-		via_iga_common_init(VGABASE);
+		via_iga_common_init(pdev, VGABASE);
 
 		/* Set palette LUT to 8-bit mode. */
 		via_iga2_set_palette_lut_resolution(VGABASE, true);
commit 341c922eb7228261151786f7665325e91b2e3ce3
Author: Kevin Brace <kevinbrace at bracecomputerlab.com>
Date:   Tue Jul 5 16:56:08 2022 -0500

    drm/via: Add DIP1 display source and I/O pad control support
    
    This applies to CLE266 chipset only.  Borrowed from OpenChrome DDX
    commit 4950b67.
    
    Signed-off-by: Kevin Brace <kevinbrace at bracecomputerlab.com>

diff --git a/drivers/gpu/drm/via/via_crtc_hw.h b/drivers/gpu/drm/via/via_crtc_hw.h
index ff3b591c8a06..d8f22114c4f6 100644
--- a/drivers/gpu/drm/via/via_crtc_hw.h
+++ b/drivers/gpu/drm/via/via_crtc_hw.h
@@ -188,6 +188,43 @@ via_dip0_set_display_source(void __iomem *regs, u8 display_source)
 			(display_source & 0x01) + 1);
 }
 
+/*
+ * Sets DIP1 (Digital Interface Port 1) I/O pad state.
+ * CLE266 chipset only.
+ */
+static inline void
+via_dip1_set_io_pad_state(void __iomem *regs, u8 io_pad_state)
+{
+	/*
+	 * 3C5.1E[5:4] - DIP1 I/O Pad Control
+	 *               00: I/O pad off
+	 *               11: I/O pad on
+	 */
+	svga_wseq_mask(regs, 0x1e, io_pad_state << 4, BIT(5) | BIT(4));
+	DRM_DEBUG_KMS("DIP1 I/O Pad State: %s\n",
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x03) ? "On" :
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x02) ? "Conditional" :
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x01) ? "Off" :
+									"Off");
+}
+
+/*
+ * Sets the display source of DIP1 (Digital Interface Port 1)
+ * interface. CLE266 chipset only.
+ */
+static inline void
+via_dip1_set_display_source(void __iomem *regs, u8 display_source)
+{
+	/*
+	 * 3X5.93[7] - DIP1 Data Source Selection
+	 *             0: IGA1
+	 *             1: IGA2
+	 */
+	svga_wcrt_mask(regs, 0x93, display_source << 7, BIT(7));
+	DRM_DEBUG_KMS("DIP1 Display Source: IGA%d\n",
+			(display_source & 0x01) + 1);
+}
+
 /*
  * Sets DVP0 (Digital Video Port 0) I/O pad state.
  */
diff --git a/drivers/gpu/drm/via/via_encoder.c b/drivers/gpu/drm/via/via_encoder.c
index a8a6c694163b..fd01176d07e4 100644
--- a/drivers/gpu/drm/via/via_encoder.c
+++ b/drivers/gpu/drm/via/via_encoder.c
@@ -41,6 +41,10 @@ void via_transmitter_io_pad_state(struct via_drm_priv *dev_priv,
 		via_dip0_set_io_pad_state(VGABASE,
 					io_pad_on ? 0x03 : 0x00);
 		break;
+	case VIA_DI_PORT_DIP1:
+		via_dip1_set_io_pad_state(VGABASE,
+					io_pad_on ? 0x03 : 0x00);
+		break;
 	case VIA_DI_PORT_DVP0:
 		via_dvp0_set_io_pad_state(VGABASE,
 					io_pad_on ? 0x03 : 0x00);
@@ -141,6 +145,9 @@ void via_transmitter_display_source(struct via_drm_priv *dev_priv,
 	case VIA_DI_PORT_DIP0:
 		via_dip0_set_display_source(VGABASE, display_source);
 		break;
+	case VIA_DI_PORT_DIP1:
+		via_dip1_set_display_source(VGABASE, display_source);
+		break;
 	case VIA_DI_PORT_DVP0:
 		via_dvp0_set_display_source(VGABASE, display_source);
 		break;
commit 4e20285a5ead274b330be0826bd58f57c944d137
Author: Kevin Brace <kevinbrace at bracecomputerlab.com>
Date:   Tue Jul 5 16:56:07 2022 -0500

    drm/via: Add DIP0 display source and I/O pad control support
    
    This applies to CLE266 chipset only.  Borrowed from OpenChrome DDX
    commit 2030c80.
    
    Signed-off-by: Kevin Brace <kevinbrace at bracecomputerlab.com>

diff --git a/drivers/gpu/drm/via/via_crtc_hw.h b/drivers/gpu/drm/via/via_crtc_hw.h
index 9cce4fdcb33a..ff3b591c8a06 100644
--- a/drivers/gpu/drm/via/via_crtc_hw.h
+++ b/drivers/gpu/drm/via/via_crtc_hw.h
@@ -151,6 +151,43 @@ via_iga1_set_hsync_shift(void __iomem *regs, u8 shift_value)
 				(shift_value & 0x07));
 }
 
+/*
+ * Sets DIP0 (Digital Interface Port 0) I/O pad state.
+ * CLE266 chipset only.
+ */
+static inline void
+via_dip0_set_io_pad_state(void __iomem *regs, u8 io_pad_state)
+{
+	/* 3C5.1E[7:6] - DIP0 Power Control
+	 *               0x: Pad always off
+	 *               10: Depend on the other control signal
+	 *               11: Pad on/off according to the
+	 *                   Power Management Status (PMS) */
+	svga_wseq_mask(regs, 0x1E, io_pad_state << 6, BIT(7) | BIT(6));
+	DRM_DEBUG_KMS("DIP0 I/O Pad State: %s\n",
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x03) ? "On" :
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x02) ? "Conditional" :
+			((io_pad_state & (BIT(1) | BIT(0))) == 0x01) ? "Off" :
+								       "Off");
+}
+
+/*
+ * Sets the display source of DIP0 (Digital Interface Port 0) interface.
+ * CLE266 chipset only.
+ */
+static inline void
+via_dip0_set_display_source(void __iomem *regs, u8 display_source)
+{
+	/*
+	 * 3X5.6C[7] - DIP0 Data Source Selection
+	 *             0: Primary Display
+	 *             1: Secondary Display
+	 */
+	svga_wcrt_mask(regs, 0x6c, display_source << 7, BIT(7));
+	DRM_DEBUG_KMS("DIP0 Display Source: IGA%d\n",
+			(display_source & 0x01) + 1);
+}
+
 /*
  * Sets DVP0 (Digital Video Port 0) I/O pad state.
  */
diff --git a/drivers/gpu/drm/via/via_encoder.c b/drivers/gpu/drm/via/via_encoder.c
index eae693fc5141..a8a6c694163b 100644
--- a/drivers/gpu/drm/via/via_encoder.c
+++ b/drivers/gpu/drm/via/via_encoder.c
@@ -37,6 +37,10 @@ void via_transmitter_io_pad_state(struct via_drm_priv *dev_priv,
 	DRM_DEBUG_KMS("Entered %s.\n", __func__);
 
 	switch(di_port) {
+	case VIA_DI_PORT_DIP0:
+		via_dip0_set_io_pad_state(VGABASE,
+					io_pad_on ? 0x03 : 0x00);
+		break;
 	case VIA_DI_PORT_DVP0:
 		via_dvp0_set_io_pad_state(VGABASE,
 					io_pad_on ? 0x03 : 0x00);
@@ -134,6 +138,9 @@ void via_transmitter_display_source(struct via_drm_priv *dev_priv,
 	DRM_DEBUG_KMS("Entered %s.\n", __func__);
 
 	switch(di_port) {
+	case VIA_DI_PORT_DIP0:
+		via_dip0_set_display_source(VGABASE, display_source);
+		break;
 	case VIA_DI_PORT_DVP0:
 		via_dvp0_set_display_source(VGABASE, display_source);
 		break;
commit d344a4c4e56fdf0e91202cb07931dfda5e22369e
Author: Kevin Brace <kevinbrace at bracecomputerlab.com>
Date:   Tue Jul 5 16:56:06 2022 -0500

    drm/via: Assign CLE266 chipset's FP to DIP1
    
    Borrowed from OpenChrome DDX commit caa49de.
    
    Signed-off-by: Kevin Brace <kevinbrace at bracecomputerlab.com>

diff --git a/drivers/gpu/drm/via/via_lvds.c b/drivers/gpu/drm/via/via_lvds.c
index acf54da4dca5..ec18710428d4 100644
--- a/drivers/gpu/drm/via/via_lvds.c
+++ b/drivers/gpu/drm/via/via_lvds.c
@@ -1150,9 +1150,14 @@ void via_lvds_probe(struct drm_device *dev)
 	/* Detect the presence of FPs. */
 	switch (chipset) {
 	case PCI_DEVICE_ID_VIA_CLE266_GFX:
+		/*
+		 * 3C5.12[4] - FPD17 pin strapping (DIP1)
+		 *             0: DVI / Capture
+		 *             1: Panel
+		 */
 		if ((sr12 & BIT(4)) || (cr3b & BIT(3))) {
 			dev_priv->int_fp1_presence = true;
-			dev_priv->int_fp1_di_port = VIA_DI_PORT_DIP0;
+			dev_priv->int_fp1_di_port = VIA_DI_PORT_DIP1;
 		} else {
 			dev_priv->int_fp1_presence = false;
 			dev_priv->int_fp1_di_port = VIA_DI_PORT_NONE;
commit 90cef58f9fa02422a63d8f8b32b8a1c99697a88e
Author: Kevin Brace <kevinbrace at bracecomputerlab.com>
Date:   Tue Jul 5 16:56:04 2022 -0500

    drm/via: Reverse CLE266 chipset's DIP0 and DIP1 assignment for DVI
    
    Borrowed from OpenChrome DDX commit 1c9de72.
    
    Signed-off-by: Kevin Brace <kevinbrace at bracecomputerlab.com>

diff --git a/drivers/gpu/drm/via/via_tmds.c b/drivers/gpu/drm/via/via_tmds.c
index df9552c362a8..41c3aca226bb 100644
--- a/drivers/gpu/drm/via/via_tmds.c
+++ b/drivers/gpu/drm/via/via_tmds.c
@@ -633,18 +633,16 @@ void via_ext_dvi_probe(struct drm_device *dev)
 	if (dev_priv->ext_tmds_presence) {
 		switch (chipset) {
 		case PCI_DEVICE_ID_VIA_CLE266_GFX:
-
-			/* 3C5.12[4] - FPD17 pin strapping
-			 *             0: TMDS transmitter (DVI) /
-			 *                capture device
-			 *             1: Flat panel */
-			if (!(sr12 & BIT(4))) {
+			/* 3C5.12[5] - FPD18 pin strapping (DIP0)
+			 *             0: DVI
+			 *             1: TV */
+			if (!(sr12 & BIT(5))) {
 				dev_priv->ext_tmds_di_port = VIA_DI_PORT_DIP0;
 
-			/* 3C5.12[5] - FPD18 pin strapping
-			 *             0: TMDS transmitter (DVI)
-			 *             1: TV encoder */
-			} else if (!(sr12 & BIT(5))) {
+			/* 3C5.12[4] - FPD17 pin strapping (DIP1)
+			 *             0: DVI / Capture
+			 *             1: Panel */
+			} else if (!(sr12 & BIT(4))) {
 				dev_priv->ext_tmds_di_port = VIA_DI_PORT_DIP1;
 			} else {
 				dev_priv->ext_tmds_di_port = VIA_DI_PORT_NONE;


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