<html> <head> <base href="https://bugs.freedesktop.org/"> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - legacy modesetting removal breaks CLE266" href="https://bugs.freedesktop.org/show_bug.cgi?id=96397#c13">Comment # 13</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - legacy modesetting removal breaks CLE266" href="https://bugs.freedesktop.org/show_bug.cgi?id=96397">bug 96397</a> from <a class="email" href="mailto:kevinbrace@gmx.com" title="Kevin Brace <kevinbrace@gmx.com>"> Kevin Brace</a> <pre>(In reply to Xavier Bachelot from <a href="show_bug.cgi?id=96397#c11">comment #11</a>) Hi Xavier, > I've reduced the needed changes to both 3d5.6b bit 7 and 3d5.6c bit 0. > Initial registers setting is 3d5.6b = 0x84 and 3d5.6c = 0x01. > Working registers setting is 3d5.6b = 0x04 and 3d5.6c = 0x00. > > According to CX700 documentation, the older chipset with doc available : > > 6b[7:6] is "First Display Channel Clock Mode Selection" > 0x: Normal > 1x: Division by 2 > > 6c[0] is "LCDCK Source Selection" > 0: LCDCK PLL output clock > 1: LCDCK PLL reference clock When I posted <a href="show_bug.cgi?id=96397#c12">comment #12</a>, you got ahead of me, and you posted <a href="show_bug.cgi?id=96397#c11">comment #11</a>. Basically, you and I were working on the same problem at the same time. (^^) I will post my CLE266 register dump I obtained around May 22nd. I do not know the version of OpenChrome that was running when I did the register dump. It was obtained with Ubuntu 10.04 LTS.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the assignee for the bug.</li> </ul> </body> </html>