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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - legacy modesetting removal breaks CLE266"
href="https://bugs.freedesktop.org/show_bug.cgi?id=96397#c11">Comment # 11</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - legacy modesetting removal breaks CLE266"
href="https://bugs.freedesktop.org/show_bug.cgi?id=96397">bug 96397</a>
from <span class="vcard"><a class="email" href="mailto:xavier@bachelot.org" title="Xavier Bachelot <xavier@bachelot.org>"> <span class="fn">Xavier Bachelot</span></a>
</span></b>
<pre>I've reduced the needed changes to both 3d5.6b bit 7 and 3d5.6c bit 0.
Initial registers setting is 3d5.6b = 0x84 and 3d5.6c = 0x01.
Working registers setting is 3d5.6b = 0x04 and 3d5.6c = 0x00.
According to CX700 documentation, the older chipset with doc available :
6b[7:6] is "First Display Channel Clock Mode Selection"
0x: Normal
1x: Division by 2
6c[0] is "LCDCK Source Selection"
0: LCDCK PLL output clock
1: LCDCK PLL reference clock</pre>
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