[Openchrome-users] slow GART memory - CN700

Wed Dec 6 11:49:55 PST 2006

Dmitri Khokhlov wrote:

>The benchmark is a user space app which measures write speed of CPU->GART->RAM. It allocates gart memory from /dev/agpgart by AGPIOC_ALLOCATE and mmaps GART range into user space. /proc/mtrr is used to cover range by mtrr. If CPU reads that RAM directly, not using GART window, speed should as fast as regular RAM access, right?
>  
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No. If the GART driver does it's mapping correctly, the RAM should be 
mapped uncached, even if you don't map it through the GART window. 
Inconsistent mappings are not allowed and will cause errors on 
processors that do speculative prefetching. This can happen:

1) CPU speculatively prefetches directly from a page in RAM and stores 
in the CPU cache.
2) You write to the same page through the GART aperture.
3) CPU decides it  doesn't need the contents in the cache and writes it 
back, overwriting the data you wrote in 2). Your data gets lost and you 
have no idea what happened.

To prevent 1) an 3) from happening, the RAM must be mapped uncached.

>Yes, it is my post on viaarena. Will this path work?: PCI device -> PCI-PCI bridge -> GART -> RAM. GART region is accessible on PCI bus (0xe8000000), right?
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Yes, I think this should work.

>About streaming PCI DMA. What destination PCI bus address should device use in this case for transfer to VIA host?
>
You get the correct address from the functions that sets up the DMA, but 
you need to write a kernel module to do this. An example on how 
streaming PCI dma is used is via_dmablit.c in the drm code.

/Thomas

> 
>Thanks
>Dmitri
>
>-----Original Message-----
>From: Thomas Hellstr?m [mailto:thomas at tungstengraphics.com] 
>Sent: Wednesday, December 06, 2006 4:52 AM
>To: Dmitri Khokhlov
>Cc: openchrome-users at openchrome.org
>Subject: Re: [Openchrome-users] slow GART memory - CN700
>
>Dmitri Khokhlov wrote:
>
>  
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>>Thomas,
>>
>>The testgart (http://dri.sourceforge.net/res/testgart.c) does cover allocated memory range with MTRR:
>>
>>reg00: base=0x00000000 (   0MB), size=1024MB: write-back, count=1
>>reg01: base=0x3c000000 ( 960MB), size=  64MB: uncachable, count=1
>>reg02: base=0xe8000000 (3712MB), size= 128MB: write-combining, count=2
>>
>>Forgot to mention, that the via video driver is not configured. vesa driver is used by default.  Could it be a problem?
>>
>>--
>>Dmitri
>> 
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>
>Nope, not really.
>
>What is the memory benchmark really doing?
>Writing to the AGP aperture should be as fast as the processor can cope with, but reading from it is dead slow. Usually around 10MiB/s. This is because the processor can't cache GART memory. Also remember that binding memory to GART has a latency of around 0.1 - 1 ms.
>
>Is it your post on VIAArena?
>If you want to access system memory from a PCI device, you should consider using streaming PCI DMA, at least if the device can handle non-contigous memory.
>
>Take a look at "Writing linux device drivers" , chapter 15:
>http://lwn.net/Kernel/LDD3/
>
>/Thomas
>
>
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>>-----Original Message-----
>>From: Thomas Hellstr?m [mailto:thomas at tungstengraphics.com]
>>Sent: Wednesday, December 06, 2006 12:04 AM
>>To: Dmitri Khokhlov
>>Cc: openchrome-users at openchrome.org
>>Subject: Re: [Openchrome-users] slow GART memory - CN700
>>
>>Dmitri Khokhlov wrote:
>>
>> 
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>>    
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>>>Hi,
>>>
>>>I have EN15000 board - C7 1.5Ghz, CN700 & VT8237R (Optimized settings 
>>>in BIOS). FC5 with kernel 2.6.17.
>>>The testgart shows extremely low memory performance:
>>>
>>>version: 0.101
>>>bridge id: 0x3141106
>>>agp_mode: 0x7000a0b
>>>aper_base: 0xe8000000
>>>aper_size: 128
>>>pg_total: 224768
>>>pg_system: 224768
>>>pg_used: 0
>>>entry.key : 0
>>>entry.key : 1
>>>Allocated 8 megs of GART memory
>>>MemoryBenchmark: 14 mb/s
>>>MemoryBenchmark: 14 mb/s
>>>MemoryBenchmark: 14 mb/s
>>>Average speed: 14 mb/s
>>>Testing data integrity (1st pass): passed on first pass.
>>>Testing data integrity (2nd pass): passed on second pass.
>>>dmesg:
>>>
>>>Linux agpgart interface v0.101 (c) Dave Jones
>>>agpgart: Detected VIA P4M800CE chipset
>>>agpgart: AGP aperture is 128M @ 0xe8000000
>>>
>>>What could be a problem here?
>>>   
>>>
>>>      
>>>
>>It looks like MTRR has not been setup correctly.
>>The DRM should do this automatically when GART memory is enabled through DRM, but I'm not sure the "testgart" application does this.
>>
>>Check the output of /proc/mtrr.
>>
>>/Thomas
>>
>>
>> 
>>
>>    
>>
>>>Thanks
>>>Dmitri
>>>
>>>----------------------------------------------------------------------
>>>-
>>>-
>>>
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