[Piglit] [Mesa-dev] [PATCH] loader/dri3: Overhaul dri3_update_num_back

Michel Dänzer michel at daenzer.net
Thu Aug 25 09:09:19 UTC 2016

On 24/08/16 06:35 AM, Eric Anholt wrote:
> Michel Dänzer <michel at daenzer.net> writes:
>> On 20/08/16 04:42 AM, Eric Anholt wrote:
>>> Michel Dänzer <michel at daenzer.net> writes:
>>>> From: Michel Dänzer <michel.daenzer at amd.com>
>>>> Always use 3 buffers when flipping. With only 2 buffers, we have to wait
>>>> for a flip to complete (which takes non-0 time even with asynchronous
>>>> flips) before we can start working on the next frame. We were previously
>>>> only using 2 buffers for flipping if the X server supports asynchronous
>>>> flips, even when we're not using asynchronous flips. This could result
>>>> in bad performance (the referenced bug report is an extreme case, where
>>>> the inter-frame stalls were preventing the GPU from reaching its maximum
>>>> clocks).
>>>> I couldn't measure any performance boost using 4 buffers with flipping.
>>>> Performance actually seemed to go down slightly, but that might have
>>>> been just noise.
>>>> Without flipping, a single back buffer is enough for swap interval 0,
>>>> but we need to use 2 back buffers when the swap interval is non-0,
>>>> otherwise we have to wait for the swap interval to pass before we can
>>>> start working on the next frame. This condition was previously reversed.
>>>> Cc: "12.0 11.2" <mesa-stable at lists.freedesktop.org>
>>>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97260
>>>> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
>>> Reviewed-by: Eric Anholt <eric at anholt.net>
>> Thanks.
>> Note that four piglit EGL tests fail with this change, but AFAICT all of
>> those tests are broken. I submitted fixes for three of them:
>> https://patchwork.freedesktop.org/patch/106809/
>> https://patchwork.freedesktop.org/patch/106807/
>> https://patchwork.freedesktop.org/patch/106808/
>> The last one is egl_chromium_sync_control. It calls eglSwapBuffers twice
>> in a row and expects that the SBC is higher than before immediately
>> after that. I.e. it expects that there is only one back buffer, so that
>> at least the second eglSwapBuffers has to block until the first swap
>> finishes. Which is no longer true with this DRI3 change. Not sure what
>> to do about this one.
> From a quick glance, change the test to wait on the SBC before querying
> the new one, maybe?

I'm not sure how to do that.

How about the attached patch? If it looks good, somebody please push it
for me.

Earthling Michel Dänzer               |               http://www.amd.com
Libre software enthusiast             |             Mesa and X developer
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