[Piglit] RFC [PATCH] shader: Test to check conditional component access in loops

[Timothy Arceri]

On 04/08/17 00:15, Gert Wollny wrote:
> Hi Brian,
> 
> thanks for the comments.
> 
> 
>>
>>> +        u.z = 0.0;
>>> +    } while (a <= n);
>>
>> Does the body of the loop need to be that complicated?
> 
> The test must achieve two things: On one hand, at least one component
> of a temporary register must be written first at the beginning of the
> loop, and another component conditionally later, but not every time.
> 
> Then the code must be complicated enough so that temporary registers
> could be merged and that the optimizer doesn't simplify the code too
> much before the merge step.
> 
> Specifically, the test should fail if the register is not tracked
> component wise in the register merge step, and it actually took me some
> time to achieve this.
> 
> I could add some comments to clarify this.

Yes please :)